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An Implementation of Automatic Boundary Scan Circuit Generator Supporting Private Instructions  

박재흥 (숭실대학교 컴퓨터학과)
장훈 (숭실대학교 컴퓨터학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 115-121 More about this Journal
Abstract
GenJTAG implemented in this paper is an automatic web-based boundary scan circuit generator. GenJTAG supports all the public instructions for the boundary scan technique, and also private instructions for other DFT techniques to be applied. Users can easily edit the generated boundary scan circuit code because it is described in behavioral level with the Verilog-HDL. GenJTAG has another advantage that any one can generate the boundary scan circuit by simply accessing to the web site.
Keywords
IEEE 1149.1; JTAG Generator; DFT; Boundary Scan; BIST;
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