• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.1
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• pp.18-22
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• 2005

We developed a new systematic calibration procedure and applied it to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity was studied under 4 different experimental conditions. Although the indium proved to be susceptible to the TED, the RTA was effective in suppressing the TED effect and in maintaining a steep retrograde profile. Just as in the case of boron, indium demonstrated significant oxidation-enhanced diffusion in silicon and its segregation coefficients at the Si/SiO₂ interface were significantly below 1. In contrast, the segregation coefficient of indium decreased as the temperature increased. The accuracy of the proposed technique has been validated by SIMS data and 0.13-㎛ device characteristics such as Vth and Idsat with errors less than 5% between simulation and experiment.

• Transactions on Electrical and Electronic Materials
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• v.5 no.6
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• pp.211-214
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• 2004

We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidationenhanced diffusion in silicon and has segregation coefficients at the $Si/SiO_2$ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data and $0.13 {\mu}m$ device characteristics such as $V_{th}$ and $Id_{sat}$ with errors less than $5 \%$ between simulation and experiment.

• Journal of the Korean Society of Propulsion Engineers
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• v.8 no.2
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• pp.95-101
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• 2004

An experimental investigation was conducted to investigate the effects of the equivalence ratio and air mass flux on the combustion efficiency in a solid fuel ramjet used fuel grains which were highly loaded with boron carbide. Combustion efficiency increased with increasing equivalence ratio (grain length), and decreasing air mass flux. Higher inlet air temperature produced higher combustion efficiencies, apparently the result of enhanced combustion of the larger boron particles those burn in a diffusion controlled regime. Short grains which considered primarily of the recirculation region produced larger particles and lower combustion efficiencies. The result of the normalized combustion efficiency increased with inlet air temperatures coincident with the result of the Brayton cycle thermal and the total efficiency relating to the heat input.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.38-45
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• 1989

We have studied the electrical characteristics of the hydrogenated amorphous silicon (a-Si:H) ambiploar thin film transistors (TET'S)using 100ppm boron-doped a-Si:H as an active layer. The enhancement of drain current due to the double injection behavior has been observed in the p-channel operation of the TFT. The drain current decreases with time in streched exponential form when the gate voltage is positive. The result indicates that the dangling bonds created by electron accumulation show identical time dependence as the diffusion of hydrogen in the film. We observed the experimental evidence that the doping efficiency changes either when the gate bias is applied or when the light is illuminated on boron-doped a-Si:H.

• ETRI Journal
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• v.35 no.4
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• pp.632-637
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• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• Nuclear Engineering and Technology
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• v.51 no.2
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• pp.369-376
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• 2019

A complete solution for a soluble-boron-free (SBF) small modular reactor (SMR) is pursued with a new burnable absorber concept, namely centrally-shielded burnable absorber (CSBA). Neutronic flexibility of the CSBA design has been discussed with fuel assembly (FA) analyses. Major design parameters and goals of the SBF SMR are discussed in view of the reactor core design and three CSBA designs are introduced to achieve both a very low burnup reactivity swing (BRS) and minimal residual reactivity of the CSBA. It is demonstrated that the core achieves a long cycle length (~37 months) and high burnup (~30 GWd/tU), while the BRS is only about 1100 pcm and the radial power distribution is rather flat. This research also introduces a supplementary reactivity control mechanism using stainless steel as mechanical shim (MS) rod to obtain the criticality during normal operation. A further analysis is performed to investigate the local power peaking of the CSBA-loaded FA at MS-rodded condition. Moreover, a simple $B_4C$-based control rod arrangement is proposed to assure a sufficient shutdown margin even at the cold-zero-power condition. All calculations in this neutronic-thermal hydraulic coupled investigation of the 3D SBF SMR core are completed by a two-step Monte Carlo-diffusion hybrid methodology.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.59-59
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• 2009

The influences of B and Si in the filler metals on microstructure and isothermal solidification during transient liquid-phase (TLP) bonding of a nitrogen-containing duplex stainless steel with MBF-30 (Ni-4.5wt.%Si-3.2wt.%B) and MBF-35 (Ni-7.3wt.%Si-2.2wt.%B), were studied at the temperature range of $1030-1090^{\circ}C$ with various times from 60 s to 3600 s under a vacuum of approximately $10^{-5}$ Torr. In case of the former, BN, $Ni_3B$ and $Ni_3Si$ precipitates were formed in the bonding region. BN and $Ni_3Si$ secondary phases were present in the joint for the latter case. The formation of $Ni_3B$ within the joint centerline is dependent on B content. The morphology of $Ni_3Si$ is dominated by Si concentration. A difference between the times for complete isothermal solidification obtained by the experiments and the conventional TLP bonding diffusion model was observed when using MBF-35. According to the simulated results, the isothermal solidification completion time for MBF-35 case was smaller than that in MBF-30. However, this experimental value obtained using MBF-35 was notably larger than that obtained using MBF-30. Isothermal solidification of liquid MBF-30 is controlled by the first isothermal solidification regime dependent on B diffusion model, whereas that of liquid MBF-35 experiences two isothermal solidification regimes and is mainly controlled by the second isothermal solidification dependent on Si diffusion model. In addition, only if Si content exceeds a critical value, the slower 2nd solidification regime will commence.

• Korean Journal of Materials Research
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• v.13 no.2
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• pp.101-105
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• 2003

In this study, we have investigated the availability of the electroless Ni-B plating for a diffusion barrier of the bus electrode. The Ni-B layer of 1$\beta$: thick was electroless deposited on the electroplated Cu bus electrode for AC plasma display. The layer was to encapsulate Cu bus electrode to prevent from its oxidation and to serve as a diffusion barrier against Cu contamination of the transparent dielectric layer in AC plasma display. The microstructure of the as-plated barrier layer was made of an amorphous phase and the structure was converted to crystalline at about 30$0^{\circ}C$. The concentration of boron was about 5∼6 wt.% in the electroless Ni-B deposit regardless of DMAB concentration. The electroless Ni-B deposit was coated on the surface of the electroplated Cu bus electrode uniformly. And the electroless Ni-B plating was found to be an appropriate process to form the diffusion barrier.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.42-51
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• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Transactions on Electrical and Electronic Materials
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• v.6 no.1
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.