• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.464-472
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• 2012

In this paper, we propose a new super-resolution algorithm that uses successive frames by applying the block matching motion estimation algorithm. Usually, single frame super-resolution algorithms are based on probability or discrete wavelet transform (DWT) approach to extract high-frequency components of the input image, but only limited information is available for these algorithms. To solve this problem, various multiple-frame based super-resolution algorithms are proposed. The accuracy of registration between frames is a very important factor for the good performance of an algorithm. We therefore propose an algorithm using 6-Tap FIR filter to increase the accuracy of the image registration with sub-pixel unit. Proposed algorithm shows better performance than other conventional interpolation based algorithms such as nearest neighborhood, bi-linear and bi-cubic methods and results in about the same image quality as DWT based super-resolution algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.71-79
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• 2010

The algorithm of multiple channel signal processing requires the flexibility of variable frequency band, efficient allocation of transmission power, and flexible frequency band reallocation to satisfy various service types which requires different transmission rates and frequency band. This paper proposes an improved multiple channel signal processing for converting the frequency band of multiple carrier signals efficiently using a window function and DFT in the time domain. In contrast to the previous algorithm of multiple-channel signal processing performing band-pass signal processing in the frequency domain, the proposed algorithm is a method of block signal processing using a window function in the time domain. In addition, the complexity of proposed algorithm of the window function is lower than that of the previous algorithm performing signal processing in the frequency domain, and it performs the frequency band transform efficiently. The computer simulation result shows that the perfect reconstruction of output signal and the flexible frequency band reallocation is performed efficiently by the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.3
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• pp.513-519
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• 2018

OFDM modulation has been used for a transmission scheme in 4G LTE (Long Term Evolution) and Wi-Fi systems to mitigate the effects of frequency selective fading channels. An OFDM modulation is a block transmission scheme because an OFDM symbol consists of multiple subcarriers with narrow bandwidth. Therefore, all OFDM symbols in a frame should be filled out with data and padding bits. Depending on the amount of data, more padding bits than information bits can occupy the last OFDM symbol. Such inefficiency causes the loss of throughput. To overcome this problem, an efficiency padding method is proposed by using the property of DFT (Discrete Fourier Transform). In the proposed method, symbol duration of the last symbol is changed depending on the number used data subcarriers in the last symbol. With numerical evaluation, it is examined that throughput enhancement achieved by the proposed method can be about 20% depending a transmission scheme and data length.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.6 s.312
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• pp.11-19
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• 2006

The recent video coding standard H.264 employs the rate-distortion optimization (RDO) method for choosing the best coding mode; however, it causes a large amount of encoding time. Thus, in order to reduce the encoding time, we need a fast mode decision algorithm. In this paper, we propose a fast inter mode decision algorithm considering quantization parameter (QP). The occurrence of best modes depends on QP. In order to reflect these characteristics, we consider the coded block pattern (CBP) which has 0 value when all quantized discrete cosine transform (DCT) coefficients are zero. We also use the early SKIP mode decision and early $16{\times}16$ mode decision methods. By computer simulations, we have verified that the proposed algorithm requires less encoding time than the fast inter mode decision method of the H.264 reference software for the Baseline and Main profiles by 19.6% and 18.8%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.41-52
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• 2009

In Motion JPEG2000 encoding, huge bandwidth requirement of data memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a new embedded compression(EC) algorithm with a little bit of image quality drop is devised. For both random accessibility and low latency, very simple and efficient entropy coding algorithm is proposed. We achieved significant memory bandwidth reductions (about 53${\sim}$81%) and reduced code-block memory to about half size through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of Korea Multimedia Society
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• v.3 no.1
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• pp.23-33
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• 2000

In this paper, we describe an algorithm which can extract human faces with natural pose from complex backgrounds. This method basically adopts the concept that facial region has the nearly same gray level for all pixels within appropriately scaled blocks. Based on the idea, we develop a hierarchial process that first, a block image data with pyramid structure of input image is generated, and some candidate regions for facial regions in the block image are Quickly determined, then finally the detailed facial features; organs are decided. To find the features easily, we introduce a local gray level transform which emphasizes dark and small regions, and estimate the geometrical triangle constraints among the facial features. The merit of our method is that we can be freed from the parameter assignment problem since the algorithm utilize a simple brightness computation, consequently robust systems not being depended on specific parameter values can be easily constructed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.4
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• pp.323-335
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• 1992

In this paper, an adaptive cosine transform coding scheme which incorporate human visual properties into the coding scheme is investigated. Human vision is relatively sensitive to mid-frequency band, and insensitive to very low and very high frequency band. These property was mathematically modelled with MTF(Modulation Transfer Function) through many psychovisual experiment. DCT transforms energy in spatial domain into frequency domain, so can exploit the MTF very efficiently. Another well-known visual characteristics is spatial masking effect that visibility of noise is less in regions of high activity than in regions of low activity. Proposed coding scheme imploys quantization matrix which represent the properties of these spatial frequency response of human vision, and adaptively quality of an image. To compute the activity index of an image block, simple operation is performed in spatial domain, and according to activity index. block of low activity region is more exactly quantized relatively than that of high activity region. Results showed that, at low bit rate, the subjective quality of the reconstructed images by proposed coding scheme is acceptible than that of coding scheme without HVS properties.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.48-57
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• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.