• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.1
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• pp.13-24
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• 2009

CLEFIA is a 128-bit block cipher which is proposed by SONY corporation and ARIA is a 128-bit block cipher which is selected as a standard cryptographic primitive. In this paper, we introduce new multiple impossible differential cryptanalysis and apply it to CLEFIA using 9-round impossible differentials proposed in [7], and apply it to ARIA using 4-round impossible differentials proposed in [11]. Our cryptanalytic results on CLEFIA and ARIA are better than previous impossible differential attacks.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.119-127
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• 2003

Impossible differential cryptanalysis(IDC) introduced by Biham et. ${al}^{[4]}$ uses impossible differential characteristics. There-fore, a security of a block cipher against IDC is measured by impossible differential characteristics. In this paper, we pro-vide a wildly applicable method to find various impossible differential characteristics of block cipher structures not using the specified form of a round function. Using this method, we can find various impossible differential characteristics for Nyberg's generalized Feistel network and a generalized RC6-like structure. Throughout the paper, we assume round functions used in block cipher structures are bijective.ctive.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.4
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• pp.709-718
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• 2019

A lightweight block cipher CHAM designed for suitability in resource-constrained environment has reasonable security level and high computational performance. Since this cipher may contain intrinsic weakness on side channel attack, it should adopt a countermeasure such as masking method. In this paper, we implement the masked CHAM cipher on 32-bit microprosessor Cortex-M3 platform to resist against side channel attack and analyze their computational performance. Based on the shortcoming of having many round functions, we apply reduced masking method to the implementation of CHAM cipher. As a result, we show that the CHAM-128/128 algorithm applied reduced masking technique requires additional operations about four times.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.3
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• pp.35-42
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• 2007

We describe the problem of reducing the key material in the Even-Mansour cipher without security degradation. Even and Mansour proposed a block cipher based on XORing secret key material just prior to and after applying random oracle permutation P such that $C=k_2\bigoplus P(M\bigoplus k_1)$. Recently, Gentry and Ramzan showed that this scheme in the random permutation oracle can be replaced by the four-round Feistel network construction in the random function oracle and also proved that their scheme is super-pseudorandom. In this paper we reduce the key size from 2n to n, which is the optimal key size of Even-Mansour cipher in the random function oracle model and also give almost the same level of security.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.860-868
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN block cipher so called SSB which has a symmetric structure in encryption and decryption. The proposed SSB is composed of the even numbers of N rounds. Each round consists of a round key addition layer, a subsitution layer, a byte exchange layer and a diffusion layer. The subsitution layer of the odd round is inverse function of one of the even round. And the diffusion layer is a MDS involution matrix. The differential and linear attack probability of SSB is $2^{-306}$ which is same with AES. The proposed symmetric SPN block cipher SSB is believed to construct a safe and efficient cipher in Smart Card and RFID environments which is in limited hardware and software resources.

• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.177-183
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• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1217-1223
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• 2020

The Block cipher CHAM is lightweight block cipher for low-end processors, developed by National Security Research Institute from Korea. The mode of operation is necessity for efficient operation of block cipher, among them, the counter (CTR) mode has good efficiency because it is easy to implement and supporting parallel operation. In this paper, we propose the optimized implementation for block cipher CHAM-CTR. The proposed implementation can be skipped some rounds by pre-computation. Thus it has better calculating speed than existing CHAM. Also, this implementation pre-load some of round keys to registers, before entering round functions. It makes reduced 160cycles loading time for round key load. Finally, proposed implementation achieved higher performance about 6.8%, and 4.5% for fixed-key scenario, and variable-key scenario, respectively.