• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1241-1246
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• 2005

본 장은 100MHz 수준의 고속 신호 샘플링을 위해 글리치 최소화 기법을 적용한 8비트 100MHz CMOS D/A 변환기 (Digital - to - Analog Converter : DAC) 회로를 제안한다. 제안하는 DAC는 0.35um Hynix CMOS 공정을 사용하여 설계 및 레이아웃을 하였으며, 응용되는 시스템의 속도, 해상도 및 면적 등의 사양을 고려하여 전류 모드 구조로 적용되었다. D/A 변환기의 선형 특성은 원래의 Spec. 과 유사하였으며, ${\pm}0.09LSB$ 정도의 DNL과 INL오차가 측정되었다. 제작된 칩 테스트 결과에 대한 오동작의 원인을 분석하였으며, 이를 통하여 칩 테스트를 위한 고려사항 등을 제안하였다.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1999년도 학술발표대회 논문집 제18권 2호
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• pp.173-176
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s for video applications. Proposed architecture is designed low power A/D converter that pipelined architecture consists of flash A/D converter. This architecture consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using $0.25{\mu}m$ CMOS technology The SNR is 76.3dB at a sampling rate of 10MHz with 3.9MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}0.5/{\pm}2$ LSB, respectively. The power consumption is 13mW at 10Msample/s.

• 한국정보통신학회논문지
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• 제6권4호
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• pp.499-504
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• 2002

본 논문에서는 열잡음과 부분대역 재밍잡음 그리고 인접한 8개의 비트 패턴에 대한 심볼간 간섭을 고려하여 FH/CPFSK 시스템의 성능을 분석하였다. 이와 같은 FH/CPFSK 시스템의 분석을 위한 파라메타 비트율(bit rate)과 변조지수를 사용하였으며, 차동검파기(Differential Detector)를 이용한 최적 수신 상관함수 제시하고, FH/CPFSK 시스템과 FH/BFSK 시스템을 비교평가 하였다. 그 결과, 근사식과 실제식의 비트 오류 확률은 높은 신호대 잡음비에서 거의 일치함을 알 수 있었고, 재밍율에 따른 성능은 차동검파를 사용한 FH/CPFSK 시스템이 리미터-변별기를 사용한 FH/CPFSK 시스템 보다 3dB 성능이 떨어지나 FH/CPFSK 시스템보다는 2dB 성능이 우수함을 입증하였다.

• 전자공학회논문지B
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• 제32B권1호
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• pp.64-72
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• 1995

We propose a new image coding method which takes into account both statistical redundancy and perceptual irrelevancy of the DCT coefficients so as to provide a high quality of the reconstructed images with a reduced transmission bit rate First, a block of DCT coefficients are decomposed into 16 subvectors so as for a subvector to convey key information about one of the low-pass or the dirctional filtered images. Then, the most significant subvector is selected as the principal edge of the block and then vector quantized. After that, the residuals of the block are computed and then sequentially quantized through aforementioned procedure until the quantization distortion is smaller than the target distortion. The proposed scheme is good at encoding images with a variety of transmission bit rates, especially at very low bit rate coding. In addition, it is another benifit of the proposed scheme that an image can be quantized with a wide range of the transmission bit rates by simply adapting the stopping criterion of the sequential vector quantizer according to the target distortion of the reconstructed image.

• The Journal of the Acoustical Society of Korea
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• 제29권3E호
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• pp.131-139
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• 2010

This paper proposes a novel spectral hole substitution technique for low bit-rate audio coding. The spectral holes frequently occurring in relatively weak energy bands due to zero bit quantization result in severe quality degradation, especially for harmonic signals such as speech vowels. The enhanced aacPlus (EAAC) audio codec artificially adjusts the minimum signal-to-mask ratio (SMR) to reduce the number of spectral holes, but it still produces noisy sound. The proposed method selectively predicts the spectral shapes of hole bands using either intra-band correlation, i.e. harmonically related coefficients nearby or inter-band correlation, i.e. previous frames. For the bands that have low prediction gain, only the energy term is quantized and spectral shapes are replaced by pseudo random values in the decoding stage. To minimize perceptual distortion caused by spectral mismatching, the criterion of the just noticeable level difference (JNLD) and spectral similarity between original and predicted shapes are adopted for quantizing the energy term. Simulation results show that the proposed method implemented into the EAAC baseline coder significantly improves speech quality at low bit-rates while keeping equivalent quality for mixed and music contents.

• 대한전자공학회논문지TC
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• 제46권4호
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• pp.64-69
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• 2009

Alamouti 직교 시공간 블록 부호(Orthogonal Space-Time Block Code; OSTBC)에 적용된 BICM(Bit Interleaved Coded Modulation)은 부호율 손실 문제를 가지고 있다. 본 논문에서는 직교 시공간 블록 부호(Orthogonal Space-Time Block Code; OSTBC)를 확장하여 확장된 OSTBC(eXpanded OSTBC; XOSTBC)를 구성하고, 여기에 비트 인터리브 된 부호화 변조(Bit Interleaved Coded Modulation; BICM)을 적용하여 부호율의 손실 없이 다이버시티 이득을 얻도록 하였다. BPSK의 경우에 대한 설계 예제와 이에 대한 모의실험 결과가 제시된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• 전자공학회논문지A
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• 제33A권4호
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• 한국통신학회논문지
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• 제9권1호
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• pp.1-10
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• 1984

時分割多重化方式에 의한 Telemetry用 PCM encoder를 塔載型遠幅測定에 適合하도록 國産化開發硏究를 追究하였다. Program switch에 의하여 選擇되는 PCM encoder의 analog人力채널은 0~64word/frame($\pm$5V full scale), discrete人力은 0~30bit(5V$\pm$1V or 0V$\pm$1V dc)이며 bit rate는 70 및 140Kbit/sec, 分解能力은 8~12bit/word를 選擇할 수 있다. 그리고 filtered output code는 5次Bessel型LPF($f_{c}$=100kHz)를 통한 NRZ-L 및 Bi$\phi$=S이며 PCM encoder의 시스템誤差는 full scale에 대하여 最大 $\pm$0.2%이다.

• 한국통신학회논문지
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• 제15권1호
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• pp.21-28
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• 1990

본 논문에서는 육사이동문선통신의 fast Rayleigh fading 채널에서 GMSK(Gaussian filered Minimum Shift Keying) 2비트 차동검파의 ISI(Intersymbol Interference)가 오류확률에 미치는 영향을 이론적으로 해석하고, 오류확률에 대한 closed form의 표현을 유도 하였다. 수치 결과는 관심의 대상이 되는 예비 변조 Gaussian 저역통과 여파기의 정규화된 대역폭 BT=0.25~0.4에 대하여 페이딩률(fading rate) $f_\rho$T를 매개 변수로 하여 나타내었다. 인접한 첫번째 비트의 ISI만을 고려한 오류확률이 GMSK 2비트 차동검파의 성능을 평가하는데 충분히 정확하다는 것을 확인하였다.