• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.443-448
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• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.1-7
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• 2004

The rapid growth of digital media and communication networks has created an urgent need for self-contained data identification methods to create adequate intellectual property right(IPR) protection technology. In this paper we propose a new watermarking method that could embed the gray-scale watermark logo in low frequency coefficients of discrete wavelet transform(DWT) domain as the marking space by using our Linear Bit-eXpansion(LBX) interleaving of gray-scale watermark, to use lots of watermark information without distortion of watermarked image quality and particularly to be robust against attack which could remove a part of image. Experimental results demonstrated the high robustness in particular against attacks such as image cropping and rotation which could remove a part of image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5C
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• pp.497-502
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• 2006

In this paper, we propose a digital image encryption method using adaptive interleaving and multiple random shuffling table to improve the existing encryption methods which use a fixed random shuffling table. In order to withstand the plaintext attack, at first, we propose a interleaving method that is adaptive to the local feature of image. Secondly, using the proposed interleaving only shuffling method and multiple shuffling method that is combined interleaving with existing random shuffling method, we encrypted image by shuffled the DPCM processed $8^*8$ blocks. Experimental results show that, the proposed algorithm is very robust to plaintext attack and there is no overhead bit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.721-727
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• 2001

In this paper, we propose a two-dimensional interleaving structure of holographic digital data storage. In this storage, many of the digital binary data are recorded, retrieved and processed in a two-dimensional data image (1000$\times$1000 bits). Therefore, burst errors in this digital device also have two-dimensional characteristics and it is required to use effective two-dimensional interleaving to overcome them. Bits of every code word should be distributed in an equilateral triangular lattice structure when they are scattered considering the random shape and occurrence of burst errors. We deal with factors and algorithm to construct this interleaving structure of equilateral triangular lattice.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• Journal of Broadcast Engineering
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• v.4 no.1
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• pp.32-43
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• 1999

This paper addresses schemes which securely transmit voice and data information under the worst communication environment using the frequency hopping(FH) communication system to avoid monitoring or interference against enemy. In case of using the conventional FEC and bit interleaving scheme. the processing time for error control coding and bit interleaving due to system complexity is highly demanded. In this paper. the effective information coding scheme of maprity error correction and block interleaving compatible to the proposed FH communication system is proposed to transmit voice or data (I6Kbps. 4.8Kbps. 2.4Kbps. 1.2Kbps, O.6Kbps) under the worst FH communication channel. In transmitter. low rate data signals are configured to majority data blocks. and transmitted repeatedly to FH channel which are structured to 20Kbps hopping frame cells. In receiver. the received data are decoded block by block, and taken majority error correction. Consequently. burst or random errors are corrected at the block deinterleaver and the majority decoder. The proposed coder structure reduces the coding/decnding processing time as well as the jamming interferences, and further simplify the data processing complexity for FH communication. Improved performance of the proposed scheme was verified under simulated channel environments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.9-17
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• 2000

In this paper we implement computer simulation system of 4FSK signal MODEM using Quadrature detector and analyze overall tranceiver system. We follow the FLEX wireless paging system standards and construct premodulation filter and data frame. We propose an efficient open loop symbol timing recovery algorithm which takes advantage of 128 bit length preamble pattern and also propose a 32 bit UW pattern which Is based on the optimal UW detection method, and excellent aperiodic autocorrelation characteristic. The BER simulation in the fading channel as well as AWGN is performed with BCH coding and Interleaving to the Quadrature detector system and it is shown that a high coding fain occurs in the fading channel rather than AWGN channel.