• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• The Journal of Korean Association of Computer Education
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• v.22 no.5
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• pp.27-37
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• 2019

In this study, for the purpose of reflection level analysis of high school students in HW design learning which is based on online simulation, we carried out 5 lessons of HW learning and analyzed there reflection levels for 5 individual time of reflection content. The reflection level analysis results for each time of learning shows that the reflection level of the $3^{rd}$ time learning of D-Flip Flop is the highest score with 1.23. The correlation analysis result between the reflection contents presents that high positive correlation between learning content and task resolving method(r=.781, p<.01), and negative design correlation between task resolving method and alternative resolving method. The HW learning satisfaction survey result shows 4.2, and most of the participant students provided opinions that the HW design learning is required and current learning contents is a bit difficult to follow. We could recognize HW design learning is required to have composition of curriculum with basic and advanced contents, and on-off lines combined.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1882-1889
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• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.529-538
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• 1992

Recently, image signal processing techniques for HDTV signal have been drastically developed. This kind of skill improvement on signal processing need specific memory device for video signal. in this paper, data latch scheme which implements CMOS flip-flop to hold Information from in-put strobe and new reading method is devised to attain a proper access time suitable for HDTY signal. Compared with conventional write scheme, data latch method has two procedures to complete write operation : bit line write and storage cell write, enabling concurrent I /0 operation at the same address. Also, fast read access is possible through the method similar to static column mode and the separated read word line.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.79-86
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• 1996

In this paper we propose an architecture for VLC(Variable Length Coder) and VLD(Variable Length Decoder) which is simple with respect to implementation point and efficient in memory. We implemented encoding and decoding circuit where we need only 7-bit address memory space for 114 MPEG1 DCT coefficients and employed minimal number of flip-flops and logics for an architecture to integrate a shift register for serial-to-parallel or parallel-to-serial conversion of the data in code mapping ROM. We obtained 50Mbps operating speed in both encoding and decoding process as the result of simulation using 0.80.8${\mu}m$ CMOS standard cells.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.