• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.4
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• pp.375-380
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• 2009

Bit error rate(BER) performance of each bit for hierarchical M-ary phase shift keying(H-MPSK) modulation scheme is changed according to the phase parameters. Thus, a method to find the phase parameters appropriate to the requests of the system is needed. In this paper, we propose a method to obtain the phase parameters from an approximate approach of BER for H-MPSK and verify a validity of the proposed method through the previously provided expression for analyzing an exact error probability of H-MPSK.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.21-28
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• 1990

In this paper, the effects of Intersymbol Interference(ISI) of Gaussian filtered minimum shift Keying (GMSK) with two-bit differential defection on the probability of error is analyzed theoretically in fast Rayleigh fading characterizing land mobile radio channels and a closed form for the probability of error is derived. Numerical results are presented for cased of interest, BT=0.25 to 0.4, taking fading rate $f_\rho$T as a parameter. It is shown that the probability of error taking the ISI of the only one adjacent bit into consideration is accurate enough to evaluate the performance of GMSK with two-bit differential detetion.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.406-411
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• 2000

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• ETRI Journal
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• v.35 no.1
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• pp.166-169
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• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1862-1867
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• 1999

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• Transactions of the Society of Information Storage Systems
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• v.6 no.1
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• pp.31-36
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• 2010

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part so fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this research, to correct errors of binary data stored in holographic data storage system, a new method for reduction errors is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers. By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise in the holographic data storage system is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2563-2578
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• 1996

In this paper, channel error characteristics are investigated to alleviate the channel error propagation problem of the digital TV transmission systems. First, error propagation problems, which are mainly caused by the inter-frame dependancy and variable length coding of the MPEG-2 baseline encoder, are intensively analyzed. Next, existing channel resilient schemes are systematically classified into two kinds of schemes; one for the encoder and the other for the decoder. By comparing the performance and implementation cost, the encoder side schemes, such as error localization, layered coding, error resilience bit stream generation techniques, are described in this paper. Also, in an effort to consider the parcticality of the real transmission situation, an efficient error detection scheme for a decoder system is proposed by employing a priori information of the bit stream syntas, checking the encoding conditions at the encoder stage, and exploiting the statistics of the image itself. Finally, subsequent error concealment technique based on the DCT coefficient recovery algorithm is adopted to evaluate the performance of the proposed error resilience technique. The computer simulation results show that the quality of the received image is significantly improved when the bit error rate is as high as 10$^{-5}$ .

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• ETRI Journal
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• v.31 no.5
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• pp.619-621
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• 2009

In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low-density parity-check coded multilevel phase-shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in-phase-quadrature mismatch, and the fading severity.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.55-61
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• 1999

A soft error rate (SER) simulator for DRAM was developed. In comparison to the other SER simulator using device simulator or Monte Carlo simulator, the proposed simulator substantially reduced the CPU time using an analytical model for the alpha-particle-induced charge collection. By analysing the soft error modes in DRAM, the bit-bar mode was identified as the main cause of soft error. Using the new SER simulator, SER of 256M DRAM was investigated and it was found that the storage capacitance had a 5fF margin.