Browse > Article
http://dx.doi.org/10.4218/etrij.13.0212.0273

Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices  

Cha, Jaewon (Department of Electrical Engineering, Yonsei University)
Kang, Sungho (Department of Electrical Engineering, Yonsei University)
Publication Information
ETRI Journal / v.35, no.1, 2013 , pp. 166-169 More about this Journal
Abstract
In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.
Keywords
Flash memory; reliability; raw bit error rate; endurance; interference; pseudorandom generator;
Citations & Related Records

Times Cited By Web Of Science : 0  (Related Records In Web of Science)
연도 인용수 순위
  • Reference
1 R. Micheloni, L. Crippa, and A. Marelli, "Inside NAND Flash Memories," Springer, 2010.
2 R.L. Galbraith and N.N. Heise, Method and Apparatus for Randomizing Data in a Direct Access Storage Device, USA Patent 4,993,029, Feb. 12, 1991.
3 R. Bez et al., "Introduction to Flash Memory," Proc. IEEE, vol. 91, no. 4, Apr. 2003, pp. 489-502.   DOI   ScienceOn
4 T.-H. Chen et al., "An Adaptive-Rate Error Correction Scheme for NAND Flash Memory," 27th IEEE VLSI Test Symp., May 2009, pp. 53-58.
5 H. Lee and E. Kim, "A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption," ETRI J., vol. 30, no. 6, Dec. 2008.
6 W. Lee, J. Kim, and B. Yu, Soild State Disk and Input/Output Method, USA Patent 2009/0300372, 2009.
7 K. Park et al., "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories," IEEE J. Solid-State Circuits, Apr. 2008, pp. 919-928.
8 K.-D Suh et al., "A 3.3 V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," ISSCC Tech. Dig., 1995, pp. 128-129.
9 C. Lee et al., "A 32-Gb MLC NAND-Flash Memory with Vth Endurance-Enhancing Schemes in 32nm CMOS," J. Solid-State Circuits, vol. 46, no. 1, Jan. 2011, pp. 97-106.   DOI   ScienceOn
10 H. Shiga and S. Fujimura, Nonvolatile Semiconductor Memory and Data Reading Method, USA Patent US2008/0239805, Oct. 2, 2008.
11 J. Cha, I. Kim, and S. Kang, "New Fault Detection Algorithm for Multi-level Cell Flash Memories," Asian Test Symp. (ATS), Nov. 2011, pp. 341-356.