• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.35-41
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• 2014

In this paper, we proposed the implementation of software-based 2D BitBLT engine on the pSOS operating system and the operation of the BitBLT engine on patient monitoring device was verified. To verify the proposed method on the patient monitoring device, we designed prototype PCB board, and verified the operation. We designed the motherboard by using ARM9-based CPU. Because hardware-based BitBLT module was replaced with software-based one, CPU load problem was weighted. To solve this problem, w changed 400Mhz processor instead of 200Mhz processor. We implemented 2D BitBLT kernel module as a device driver which is one of the key elements of a graphics controller GUI in patient monitoring device.

• The Journal of Internal Korean Medicine
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• v.25 no.4
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• pp.274-288
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• 2004

Objectives : This study was designed to evaluate the effect on cytotoxicity of Bojungikki-tang(BIT) in human lung cancer H460 cells. Methods : BIT-induced cell death was confirmed as apoptosis characterized by chromatin condensation and increase of the $sub-G_1$, DNA content. It was tested whether the water extract of BIT affects the cell cycle regulators such as, p2l/Cipl, p27/Kipl, cyclin $B_1$. Results : The data showed that treatment of BIT decreased the viability of H460 cells in a dose-dependent manner. p2l/Cip1 is gradually decreased by the addition of the cells with BIT extract. Interestingly, p27/Kip1 is not detected for 24 hr after the addition of BIT extract, however, after 24 hr, p27/Kipl markedly increased. In addition, cyclin $B_1$, decreased in a time dependent manner after the addition of the water extract. The activation of caspase -3 protease was further confirmed by degradation of procaspase-8 protease andpoly(ADP-ribose) polymerase(P ARP) by BIT in H460 cells. Moreover, BIT induced the increase of Bak expression. Conclusion : These results suggest that the extract of BIT exerts anticancer effects to induce the death of human lung cancer H460 cells via down regulation of cell cycle regulators such as p2l/Cip1, and cyclin B1 or up regulation of cell cycle regulators such as p27/Kip1. Moerover results suggest that BIT induces an apoptosis in H460 cells via activation of intrinsic caspase cascades.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.11
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• pp.5381-5399
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• 2016

Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.1-6
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• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.6
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• pp.60-66
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• 2021

The core is extracted through drilling and used to evaluate the feasibility of developing mineral resources. To extract the core, a bit is installed in the forefront of the drilling device for drilling. Here, the drill bit receives stress due to direct friction against the ground. In addition, a bit appropriate for the given ground condition should be used due to the possibility of damaging a bit as a result of friction. This paper used a current bit model based on an impregnated bit and analyzed a new bit model that uses a stiffener of similar/disparate materials. The hardness and deflective strength were then evaluated by modeling the shape of impregnated bit through a calculation based on a theoretical formula. Through FEM analysis of the existing model and the new model, the stress and strain calculation results were optimized to minimize the stress and strain with a stress of 1.92 × 107 Pa and a strain of 9.6× 10-5 m/m.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.71-73
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• 1998

새로운 DEC Alpha, MINPS R40001[1], PowerPC등과 같은 64-bit 마이크로프로세서는 운영체제와 응용프로그램에 매우 광활한 64-bit 주소공간(wide address system)을 제공한다. 64-bit 주소공간은 중소규모 분산 컴퓨터 시스템의 모든 데이터를 포함할 수 있는 크기이다. 이 64-bit 주소공간은 32-bit 주소공간과 다른 방법으로 활용하는 것을 가능하게 해주었다. 지금까지의 시스템과는 달리 WAS(wide address system)에서는 모든 프로세서들이 하나의 주소공간을 공유함으로서 프로세서간 자료의 공유 및 통신이 간편하게 이루어 질 수 있다. 공유된 광활한 64-bit 주소공간의 상용방안은 WAS 시스템 연구에서 매우 중요하다. 본 논문에서는 WAS 시스템의 보다 구현하기 쉬운 64-bit 주소공간의 설계에 대해서 제안한다.

• Journal of Advanced Navigation Technology
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• v.11 no.4
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• pp.388-393
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• 2007

In designing transform coders bit allocation is one of the important issues. In this paper we propose two optimal algorithms for integer bit allocation in transform coding. Based on high-resolution formulas for bit allocation, the most and least greedy algorithms are developed to optimally adjust non-integer bit rates of coefficient quantizers to integer values. In particular, a duality property is observed between the two greedy algorithms.

• ETRI Journal
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• v.24 no.4
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• pp.280-289
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• 2002

In this work, we present a novel approach to the bit allocation problem that aims to minimize overall distortion subject to a bit rate constraint. The optimal solution can be found by the Lagrangian method with dynamic programming. However, the optimal bit allocation for block-based interframe coding is practically unattainable because of the interframe dependency of macroblocks caused by motion compensation. To reduce the computational burden while maintaining a result close to the optimum, i.e., near optimum, we propose an alternative method. First, we present a partitioned form of the bit allocation problem: a "frame-level problem" and "one-frame macroblock-level problems." We show that the solution to this new form is also the solution to the conventional bit allocation problem. Further, we propose a bit allocation algorithm using a "two-phase optimization technique" with an interframe dependency model and a rate-distortion model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.2
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• pp.724-737
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• 2020

Corrected Block TEA(or XXTEA) is a block cipher designed to correct security weakness in the original block TEA in 1998. In this paper, XXTEA cipher hardware which can encrypt or decrypt between 64-bit and 256-bit messages using 128-bit master key is implemented. Minimum message block size is 64-bit wide and maximal message block size is 256-bit wide. The designed XXTEA can encrypt and decrypt variable-length message blocks which are some arbitrary multiple of 32 bits in message block sizes. XXTEA core of this paper is described using Verilog-HDL and downloaded on Vertex4. The operation frequency is 177MHz. The maximum throughput for 64-bit message blocks is 174Mbps and that of 256-bit message blocks is 467Mbps. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.