• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.5
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• pp.1005-1009
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• 2010

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.4
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• pp.45-52
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• 1980

In order to eliminate the phase errors caused by the finite GB product of operational amplifiers, novel integnator circuits are proposed. These circuits are characterized by their positive phase error angles and integrator selectivity. The positive sign of the Q and of the circuits compensates the negative selectivity and phase error angles, inherent in the integrated operational amplifiers. Miller inverting intergrator of a biquad circuit realized by Thomas is replaced by the proposed circuit and the band-pass frequency response of the modified biquad network is experimentally analyzed. A considerable improvement is recognized to such extent that the center frequency of the band-pass filter is allowed to be shifted up to 20KHz, which has been infeasible with conventional biquad networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2395-2402
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• 2013

An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1436-1441
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• 1990

Prototype Switched Capacitor 4th order Low pass and Band Pass Filters were Realized and tested. Their capacitor values were determined by using automatic SCF design tool. Each filter was designed to operate in voiceband frequency, and practical solutions to improve its frequency characteristics were given. Experimental results show the validity of automatic SCF design program. Simulation and experimental results were fully compared and optimum design conditions were summarized.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.143-148
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• 2015

In this paper a new method is proposed for realizing active floating inductors from voltage differencing transconductance amplifier(VDTA) which is being studied nowadays. This proposed method employs only one VDTA and one transconductance for designing an active inductor from a passive floating inductor and implementing it to integrated circuits. The number of CMOS transistors can be considerably reduced from 6~18 as 1~3 gm circuits can be eliminated and even without R the design can be made, which can help in reducing the size of the circuit and power consumption. The proposed VDTA floating inductor was successfully used in constructing 1 MHz second order biquad active bandpass filter and bandwidth could be adjusted from 77kHz~1.59MHz by the changes made in gm from 6uS~20uS.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.743-746
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• 2002

This paper proposes the design of a current-mode CCII-based 2$\^$nd/ _order bandpass biquad filter from a grounded series capacitor and frequency-dependent negative conductor ( C-D ) immittance function simulator using the macro model of a commercial available CCII+, AD844, from Analog Devices, Inc. The results are compared with the other results those are designed using ideal model of CCII-. The gain and phase deviations; due to the effects of passive sensitivity, active sensitivity, gain sensitivity and component variability; are considered using Monte-Carlo analysis of PSpice program.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3127-3129
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• 2000

본 논문에서는 광 다이오드에서 들어오는 신호로부터 원하는 대역의 신호를 얻기 위한 적외선 수신 IC에 적합한 대역통과필터를 설계하였다 설계한 대역통과필터는 2차 Biquad gm-C 필터의 구조를 이용하여 중심주파수가 38kHz. Quality factor가 10인 필터를 구현하였다. 구현된 대역통과필터는 필터부분과 중심주파수를 보정해 주는 frequency tuning 부분으로 구성되어 있다. 낮은 transconductance와 높은 선형성을 요구하는 transconductor의 설계를 위해 Gilbert 곱셈기 특성을 이용하여 구현하였고 AMS사의 0.8${\mu}m$ BiCMOS model을 사용하여 +5V로 동작되도록 설계 하였다

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.29-34
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• 1999

In this paper, a current comparative frequency automatic tuning circuit for the CMOS gm-C bandpass filters are designed with the new architecture. And also, when the designed circuit is compared to the typical tuning circuit, the designed circuit has very simple architecture that is composed of the current comparator and charge pump and operating in 3V power supply. The proposed tuning circuit automatically compensates the difference between the operating current of the transconductor and the specified reference Current. Using CMOS 0.8um parameter a biquad gm-C bandpass filter with center frequency($f_\circ$=60MHz) is designed, and according to the transistor size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operation of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.49-58
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• 1999

This paper describes an integrated low pass filter fabricated by using $0.8{\mu}m$ single poly CMOS ASIC technology. The filter has been designed for a 5th-order elliptic switched capacitor filter with cutoff frequency of 5khz, 0.1dB passband ripple. The filter consists of MOS swiches poly capacitors and five CMOS op-amps. For the realization of the SC filter, continuous time transfer function H(s) is obtained from LC passive type, and transfered as discrete time transfer H(z) through bilinear-z transform. Another filter has been designed by capacitor scaling for reduced chip area, considering dynamic range of the op-amp. The test results of two fabricated filters are cutoff frequency of 4.96~4.98khz, 35~38dB gain attenuation and 0.72~0.81dB passband ripple with the ${\pm}2.5V$power supply clock of 50KHz.