• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.9 no.4
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• pp.141-146
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• 2010

In this paper, bandgap reference PTAT(Proportional to Absolute Temperature) circuit and flexible gain control of LNA(Low Noise Amplifier) which is usable in Zigbee system of 2.4GHz band are designed by TSMC $0.18{\mu}m$ CMOS library. PTAT bandgap reference circuit is proposed to minimize the instability of CMOS circuit which may be unstable in temperature changes. This circuit is designed such that output voltage remains within 1.3V even when the temperature varies from $-40^{\circ}C$ to $-50^{\circ}C$ when applied to the gate bias voltage of LNA. In addition, the LNA is designed to be operated on 2.4GHz which is applicable to Zigbee system and able to select gains by changing output impedance using 4 NMOS operated switches. The simulation result shows that achieved gain is 14.3~17.6dB and NF (Noise Figure) 1.008~1.032dB.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.121-124
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• 2006

It is widely know that one of the most important tasks is the research of plasma for the purpose o nuclear fusion, is to make a stable confinement of high ${\beta}$ value plasma. And, for making the stable confinement, pinch pl-asma produced by reversed field has been mainly studied yet. Magnetic field has been used to hold plasma at high temperature for a long time. Reverse field has shown unstable process. Using ratio frequency, the author could control the instability of the process and formed a stable erversed field. Inthe experiment let a reversed field configuration from by adding-Bias field in advance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.139-144
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• 2013

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2187-2189
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• 2005

It is widely know that one of the most important tasks is the research of plasma for the purpose o nuclear fusion, is to make a stable confinement of high ${\beta}$ value plasma. And, for making the stable confinement, pinch p1-asma produced by reversed field has been mainly studied yet. Magnetic field has been used to hold plasma at high temperature for a long time. Reverse field has shown unstable process. Using ratio frequency, the author could control the instability of the process and formed a stable erversed field. Inthe experiment let a reversed field configuration from by adding-Bias field in advance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.29-30
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide ($SiO_2$) under both Negative-bias Temperature Instability(NBTI) and Hot-carrier-induced(HCI) stresses using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (1~5 atm.). Statistical parameter variations depend on the stress conditions. We suggest that deuterium bonds in $SiO_2$ film is effective in suppressing the generation of traps related to the energetic hot electrons.

• Convergence Security Journal
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• v.24 no.3
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• pp.59-65
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• 2024

This research proposes an accelerated aging test procedure for Static Random Access Memory Physically Unclonable Functions (SRAM PUFs). PUFs utilize semiconductor process variations to serve as a hardware security feature, akin to semiconductor device fingerprints. Thus, the proposed accelerated aging test simulates a semiconductor's 10-year lifecycle, enabling the prediction of PUF characteristics after a decade of use, which is crucial for verifying the safety and stability of SRAM PUFs. This research introduces test procedures that simulate 10 years of aging in approximately 9 days by setting temperature and voltage higher than operational environments. These procedures allow for the quantitative evaluation of SRAM PUF characteristics. This research is expected to contribute to the advancement of design and maintenance testing techniques for systems based on SRAM PUFs.

• Atmosphere
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• v.26 no.1
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• pp.141-158
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• 2016

The objective of this study is to examine the impact of urban canopy and the horizontal resolution on simulated meteorological variables such as 10-m wind speed, 2-m temperature and precipitation using WRF model for a local, convective rainfall case. We performed four sensitivity tests by varying the use of urban canopy model (UCM) and the horizontal resolution, then compared the model results with observations of AWS network. The focus of our study is over the Seoul metropolitan area for a convective rainfall that occurred on 16 August 16 2015. The analysis shows that mean diurnal variation of temperature is better simulated by the model runs with UCM before the convective rainfall. However, after rainfall, model shows significant difference in air temperature among sensitivity tests depending on the simulated rainfall amount. The rainfall amount is significantly underestimated in 0.5 km resolution model run compared to 1.5 km resolution, particularly over the urban areas. This is due to earlier occurrence of light rainfall in 0.5 km resolution model. Earlier light rainfall in the afternoon eliminates convective instability significantly, which prevents occurrence of rainfall later in the evening. The use of UCM results in a higher maximum rainfall in the domain, which is due to higher temperature in model runs with urban canopy. Earlier occurrence of rainfall in 0.5 km resolution model is related to rapid growth of PBL. Enhanced mixing and higher temperature result in rapid growth of PBL, which provides more favorable conditions for convection in the 0.5 km resolution run with urban canopy. All sensitivity tests show dry bias, which also contributes to the occurrence of light precipitation throughout the simulation period.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.170-170
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• 2012

최근 주목받고 있는 amorphous InGaZnO (a-IGZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT (a-Si;H)에 비해 비정질 상태에서도 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭에 의해 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광 소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 하지만, 실제 디스플레이가 동작하는 동안 스위칭 TFT는 백라이트 또는 외부에서 들어오는 빛에 지속적으로 노출되게 되고, 이 빛에 의해서 TFT 소자의 신뢰성에 악영향을 끼친다. 또한, 디스플레이가 장시간 동안 동작 하면 내부 온도가 상승하게 되고 이에 따른 온도에 의한 신뢰성 문제도 동시에 고려되어야 한다. 특히, 실제 AM-LCD에서 스위칭 TFT는 양의 게이트 전압보다 음의 게이트 전압에 의해서 약 500 배 가량 더 긴 시간의 스트레스를 받기 때문에 음의 게이트 전압에 대한 신뢰성 평가는 대단히 중요한 이슈이다. 스트레스에 의한 문턱 전압의 변화는 게이트 절연막과 반도체 채널 사이의 계면 또는 게이트 절연막의 벌크 트랩에 의한 것으로 게이트 절연막의 선택에 따라서 신뢰성을 효과적으로 개선시킬 수 있다. 본 연구에서는 적층된 $Si_3N_4/SiO_2$ (NO 구조) 이중층 구조를 게이트 절연막으로 사용하고, 완충층의 역할을 하는 $SiO_2$막의 두께에 따른 소자의 전기적 특성 및 신뢰성을 평가하였다. a-IGZO TFT 소자의 전기적 특성과 신뢰성 평가를 위하여 간단한 구조의 pseudo-MOS field effect transistor (${\Psi}$-MOSFET) 방법을 이용하였다. 제작된 소자의 최적화된 $SiO_2$ 완충층의 두께는 20 nm이고 $12.3cm^2/V{\cdot}s$의 유효 전계 이동도, 148 mV/dec의 subthreshold swing, $4.52{\times}10^{11}cm^{-2}$의 계면 트랩, negative bias illumination stress에서 1.23 V의 문턱 전압 변화율, negative bias temperature illumination stress에서 2.06 V의 문턱 전압 변화율을 보여 뛰어난 전기적, 신뢰성 특성을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.