• 제목/요약/키워드: band-to-band tunneling

검색결과 82건 처리시간 0.024초

L형 터널 트랜지스터의 트랩-보조-터널링 현상 조사 (Investigation of Trap-Assisted-Tunneling Mechanism in L-Shaped Tunneling Field-Effect-Transistor)

  • 파라즈 나잠;유윤섭
    • 한국정보통신학회:학술대회논문집
    • /
    • 한국정보통신학회 2018년도 추계학술대회
    • /
    • pp.512-513
    • /
    • 2018
  • 트랩-보조-터널링(Trap-Assisted-Tunneling; TAT)은 실제 터널링 전계 효과 트랜지스터 (TFET)의 임계 이하 기울기를 저하시키고 시뮬레이션에서 고려되어야한다. 그러나, 그 메커니즘은 라인 터널링 타입 L형 TFET(LTFET)에서는 잘 알려져 있지 않았다. 본 연구는 dynamic nonlocal Schenk 모델을 이용한 LTFET의 TAT 메커니즘을 연구한다. 이 연구에서는 터널링 이벤트를 위해서 phonon assisted and direct band가 모두 고려되었다.

  • PDF

Gate-Induced-Drain-Leakage (GIDL) Current of MOSFETs with Channel Doping and Width Dependence

  • Choi, Byoung-Seon;Choi, Pyung-Ho;Choi, Byoung-Deog
    • 한국진공학회:학술대회논문집
    • /
    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
    • /
    • pp.344-345
    • /
    • 2012
  • The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

  • PDF

Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

  • Shin, Sunhae;Kang, In Man;Kim, Kyung Rok
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제13권6호
    • /
    • pp.546-550
    • /
    • 2013
  • We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

저전압 EEPROM IP용 DC-DC Converter 설계 (Design of DC-DC Converter for Low-Voltage EEPROM IPs)

  • 장지혜;최인화;박영배;김려연;하판봉;김영희
    • 한국정보통신학회:학술대회논문집
    • /
    • 한국정보통신학회 2012년도 추계학술대회
    • /
    • pp.852-855
    • /
    • 2012
  • 본 논문에서는 FN(Fowler-Nordheim) 터널링 방식에 의한 program 동작과 band-to-band 터널링 방식에 의한 erase 동작을 수행하는 EEPROM IP용 DC-DC converter를 설계하였다. 로직전압으로 $1.5V{\pm}10%$의 저전압을 사용하는 EEPROM IP용 DC-DC converter는 charge pump 회로의 pumping stage 수와 pumping capacitance를 줄이기 위해 입력 전압으로 VDD 대신 VRD(Read Voltage)을 전압을 사용하는 방식을 제안하였다. VRD($=3.1V{\pm}0.1V$)는 5V의 external supply voltage를 voltage regulator 회로를 이용하여 regulation된 전압이다. 설계된 DC-DC converter는 write 모드에서 VPP(=8V)와 VNN(=-8V)의 전압을 출력한다.

  • PDF

$Hg_{1-x}Cd_{x}$Te 광다이오드에서 터널링 전류가 RoA에 미치는 영향 (Tunneling Current Contribution to RoA of $Hg_{1-x}Cd_{x}$Te Photodiodes)

  • 박장우;곽계달
    • 전자공학회논문지A
    • /
    • 제29A권10호
    • /
    • pp.42-48
    • /
    • 1992
  • RoA is an important figure of merits for estimating the performance of p-n junction infrared detectors. This paper presents the tunneling current contribution to RoA of $Hg_{1-x}Cd_{x}$Te n$^{+}$-p juction photodiodes. Then, a diffusion model, a thermal generation-recombination model, an indirect tunneling model via trap, and a band-to-band direct tunneling model are considered to calculate RoA. Using these models, RoA depending on temperature, doping concentration, and mole fraction is calculated. Also from these results, under various operating conditions the dominant dark current mechanisms cna be understood.

  • PDF

Analysis of Flat-Band-Voltage Dependent Breakdown Voltage for 10 nm Double Gate MOSFET

  • Jung, Hakkee;Dimitrijev, Sima
    • Journal of information and communication convergence engineering
    • /
    • 제16권1호
    • /
    • pp.43-47
    • /
    • 2018
  • The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

포켓 구조 터널링 전계효과 트랜지스터의 2D 터널링 효과 (2D Tunneling Effect of Pocket Tunnel Field Effect Transistor)

  • 안태준;유윤섭
    • 한국정보통신학회:학술대회논문집
    • /
    • 한국정보통신학회 2017년도 추계학술대회
    • /
    • pp.243-244
    • /
    • 2017
  • 이 논문은 터널링 전계효과 트랜지스터의 밴드 간 터널링 전류 계산에 대하여 1차원과 2차원 방향의 터널링이 어떤 차이를 나타내는지 알아보았다. 2차원 방향의 터널링은 1차원 방향의 터널링에서 계산 되지 않는 대각선 방향의 터널링이 나타나기 때문에 더 정확한 터널링 전류를 계산할 수 있다. 시뮬레이션 결과는 문턱전압 이상의 전압에서는 2차원 방향으로 일어나는 터널링이 큰 영향을 미치지 않지만, 문턱전압 이하에서는 문턱전압 이하 기울기에 많은 영향을 미친다.

  • PDF

Inclusion of Silicon Delta-doped Two-dimensional Electron Gas Layer on Multi-quantum Well Nano-structures of Blue Light Emitting Diodes

  • Kim, Keun-Joo
    • Transactions on Electrical and Electronic Materials
    • /
    • 제5권5호
    • /
    • pp.173-179
    • /
    • 2004
  • The influence of heavily Si impurity doping in the GaN barrier of InGaN/GaN multi-quantum well structures of blue light emitting diodes were investigated by growing samples in metal-organic chemical vapor deposition. The delta-doped sample was compared to the sample with the undoped barrier. The delta-doped sample shows the tunneling behavior and forms the energy level of 0.32 eV for tunneling and the photoemission of the 450-nm band. The photo-luminescence shows the blue-shifted broad band of the radiative transition due to the inclusion of Si delta-doped layer indicating that the delta doping effect acts to form the higher energy level than that of quantum well. The dislocation may provide the carrier tunneling channel and plays as a source of acceptor. During the tunneling of hot carrier, there was no light emission.

Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate

  • Ali, Asif;Seo, Dongsun;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제17권1호
    • /
    • pp.156-161
    • /
    • 2017
  • This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

분석 조건에 따른 p-MOSFET의 게이트에 유기된 드레인 누설전류의 열화 (Degradation of Gate Induced Drain Leakage(GIDL) Current of p-MOSFET along to Analysis Condition)

  • 배지철;이용재
    • E2M - 전기 전자와 첨단 소재
    • /
    • 제10권1호
    • /
    • pp.26-32
    • /
    • 1997
  • The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

  • PDF