• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.1
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• pp.51-57
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• 2009

Blind equalization techniques have been widely used in wireless communication systems. In this paper, we investigate the information potentials in the criterion of minimizing Euclidian distance between two PDFs criterion for adaptive blind equalizers and evaluate BER performance of the method that has utilized an appropriate balance between the two information potentials, one from output samples and ramdomly generated desired samples at the receiver and another from the interactions among output samples. The balanced information potential method has shown in the BER performance results that it can produce significantly enhanced BER performance in blind equalization applications.

• Journal of Power Electronics
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• v.14 no.2
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.115-121
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• 2015

Stand-alone inverter supplies constant voltage to loads. However, when a three-phase stand-alone inverter supplies unbalanced load, the generated output voltages also become unbalanced. The nonlinear characteristics of inverter dead time cause a more serious distortion in the output voltage. With unbalanced load, voltage distortion caused by dead time differs from voltage distortion under balanced load. Phase voltages in the stationary reference frame include unbalanced odd harmonics and then, d-q axis voltages in the synchronous reference frame have even harmonics with different magnitude, which are mitigated by the proposed multiple resonant controller. This study analyzes the voltage distortion caused by unbalanced load and dead time, and proposes a novel dead time compensation method. The proposed control method is tested on a 10-kW stand-alone inverter system, and shows that total harmonic distortion (THD) is reduced to 1.5% from 4.3%.

• Journal of Power Electronics
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• v.17 no.1
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• pp.181-189
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• 2017

The three-phase four-leg voltage-source inverter topology is an interesting option for the three-phase four-wire system. With an additional leg, this topology can achieve superior performance under unbalanced and nonlinear load conditions. However, because of the low bandwidth of conventional controllers in high-power inverter applications, the system cannot guarantee a balanced output voltage under the unbalanced load condition. Most of the methods proposed to solve this problem mainly use the multiple synchronous frame method, which requires several controllers and a large amount of computation because of frame transformation. This study proposes a simple hybrid controller that combines proportional-integral (PI) and resonant controllers in the synchronous frame synchronized with the positive-sequence component of the output voltage of the three-phase four-leg inverter. The design procedure for the controller and the theoretical analysis are presented. The performance of the proposed method is verified by the experimental results and compared with that of the conventional PI controller.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.2
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• pp.253-257
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• 2016

This paper analyzes voltage control method in order to supply high-quality power for stand-alone microgrid. Stand-alone microgrid is composed of battery bank, stand-alone PCS and controllable loads. The main role of stand-alone PCS is to supply high-quality power to loads as main source by using stable voltage method regardless of load conditions. In particularly, output voltage of stand-alone PCS gets severely unbalanced voltage under unbalanced loads. Fundamental positive and negative sequences are transformed by two coordinates transformation which are rotated in each opposite direction, respectively. Each fundamental d-q voltage is regulated by each fundamental PI control. In addition, low-order harmonics are compensated through resonant controllers. Performance of stand-alone microgrid is tested for feasibility, and it is verified that output voltage of THD is improved to 1% from 2.2% under 50 kW balanced load, and is improved to 1.1% from 2.6% under 50 kW unbalanced load.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.1071-1079
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• 2010

This paper describes the design and fabrication of a high-efficiency GaN HEMT(Gallium Nitride High-electron Mobility Transistor) Pallet power amplifier module for S-band phased array radar applications. Pallet amplifier module has a series 2-cascaded power amplifier and the final amplification-stage consists of balanced GaN HEMT transistor. In order to achieve high efficiency characteristic of pallet power amplifier module, all amplifiers are designed to the switching-mode amplifier. We performed with various PRF(Pulse Repetition Frequency) of 1, 10, 100 and 1000Hz at a fixed pulse width of $100{\mu}s$. In the experimental results, the output power, gain, and drain efficiency(${\eta}_{total}$) of the Pallet power amplifier module are 300W, 33dB, and 51% at saturated output power of 2.9GHz, respectively.

• Journal of Power Electronics
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• v.14 no.4
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.5
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• pp.425-438
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• 2015

This study proposes a three-stage model of R&BD performance which captures commercialization outcomes as well as conventional R&D performance. The model is composed of three factors : inputs (R&D budgets and researchers), outputs (patents and papers), and outcomes (technical fees, products sales, and cost savings). Three stages are defined for each transformation process between the three factors : efficiency stage from input to output (stage 1), effectiveness stage from output to outcome (stage 2), and productivity stage from input to outcome (stage 3). The performance of each stage is measured by data envelopment analysis (DEA). DEA is a non-parametric efficiency measurement technique that has widely been used in R&D performance measurement. We measure the performance of 171 projects of 6 public R&BD programs managed by Seoul Business Agency using the proposed three-stage model. In order to provide a balanced and holistic view of R&BD performance, the R&BD performance map is also constructed based on performance of efficiency and productivity stages.

• Journal of Power Electronics
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• v.18 no.1
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.