• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.410-424
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• 1993

In this paper, we present new techniques for designing systolic arrya and asynchronous arrays for digital-signal processings. More specifically, we propose a systolic array with simple local interconnections which achieves optimal performance without having undesirable features such as preloading input data or global broadcasting. As asynchronous array for digital-signal processings, which can speed up the total computation time significantly is also which can speed up the total computation time significantly is also presented. The key component of the asynchronous array is a presented. The key component of the asynchronous array is a comunicaiton protocol which controls input data flow properly and efficiently. Finally, performance of the arrays is analyzed and a simulation using Occam programmed in a Transputer network is reported.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.5
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• pp.9-17
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• 2010

Corrective control compensates the stable-state behavior of asynchronous sequential machines so that the closed-loop system can be changed in a desirable way. Using corrective control, we present a novel fault tolerance scheme that overcomes permanent faults for asynchronous sequential machines. When a permanent fault occurs to an asynchronous machine, the fault is not recovered forever while the machine is irreversibly stuck in a set of failure states. But, if the machine has control redundancy in the limited behavior range, corrective control can be applied to solve the fault tolerance problem against permanent faults. We present the condition on detecting permanent faults and the existence condition of an appropriate corrective controller. The design procedure for the proposed controller is described in a case study.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2011.10a
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• pp.73-73
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• 2011

In fact, asynchronous motors are used widely. Asynchronous motors which have large power (compared to the source supplies) is needed to start them in various methods. The theory of application reduced voltage to motor's stator or variable resistor fed rotor for the purpose of altering the motor's torque and power consumption characteristics is an idea that has existed for many years. These concepts have flourished mainly due to the need to limit torque and limited generator/power distribution capabilities. However, how can know exactly the time of switching steps with different types of motors as well as load characteristics is very difficult. This paper focuses on the design and development mathematical models of motor[1][2], load, ACB, asynchronous machine and then is implemented in SIMULINK in order to calculate this time, special on ships where power generation station is limited. The simulation results are both compared and discussed in detail so that it can apply to conclude the most suitable and applicable starting time for new system with various motors and load.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.1002-1008
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• 2003

In terrestrial data broadcasting, we are just on the beginning stage in all aspects including implementation and design techniques and only asynchronous data processing has been receiving a little study. In this paper, we therefore propose an efficient processing algorithm for synchronization of asynchronous data by using trigger information to make more diverse service possible with a variety of contents. In the proposed algorithm, trigger data is encapsulated in DSM-CC section and transmitted in a form of MPEG-2 TS. The data is then separated in PC type set-top box and detached asynchronous data and trigger data are stored by the proposed algorithm. Pre-loaded asynchronous data is displayed when STC(system time clock) has the same value as PTS(presentation time stamp). Proper operation of the proposed algorithm was verified by using a content of asynchronous data with extensible markup language(XML) and a declarative application(DA) browser.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.963-966
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• 2001

The wideband DS-CDMA (W-CDMA) system is one of the candidates for the next generation mobile communication system known as IMT-2000. The important concept of W-CDMA is the introduction of intercell asynchronous operation. In this paper, we design and analyze the system level simulator for the International Mobile Tele communication - 2000 (IMT-2000) 3-rd generation partnership project (3GPP) system. We confirm how the simulator works by BER over different Eb/NO. This study will be expected to use as reference data in the development of asynchronous IMT-2000. In this paper, we analyze a physical layer of W-CDMA system and design a transmitter and receiver by using ADS (Advanced Design System). Also, we simulated a link level performance in Rayleigh fading channel environment. This study will be useful in the analysis and design of W-CDMA system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2021-2026
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• 2007

In the parer, we design a non-coherent UWB system by adopting the architecture of a simplified asynchronous transmission and the edge-triggered pulse transmission, which makes e system performance independent of the share of the transmitted waveform, robust to multipath channels. The designed non-coherent UWB transceiver architecture has an advantage of the simple realization since any mixer, high-speed correlator, and high-sampling A/D converter are not necessary at the cost of performance degradation of about 3dB. Further, the designed non-coherent UWB transceiver is actually implemented with the wireless CANVAS prototype testbed in short range indoor application environments such as a lecture room. The implemented prototype testbed is proven to offer the data rate of 115kbps on the conditions of Peer-to-Peer(P-to-P) in the indoor channel within the range of about 10m.