• Journal of KIISE:Software and Applications
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• v.31 no.6
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• pp.773-783
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• 2004

This paper presents a method for real-time verification of Statecharts. Statecharts has been widely used for real-time reactive systems, and supports two time models: synchronous and asynchronous. However, existing real-time verification methods for them are incompatible with the asynchronous time model or increase state space by introducing new variables to the target models. We solved these problems by extending existing model checking algorithms. The extended algorithms can be used with both time models of Statecharts because they consider time increasing transitions only. In addition, they do not increase target state space since they count those transitions internally without additional variables. We extended an existing model checker, NuSMV, based on the proposed algorithms and conducted some experiments to show their advantage.

• Journal of Astronomy and Space Sciences
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• v.31 no.3
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• pp.235-240
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• 2014

The communications link in a space program is a crucial point for upgrading its performance by handling data between spacecraft bus and payloads, because spacecraft's missions are related to the data handling mechanism using communications ports such as a controlled area network bus (CAN Bus) and a universal asynchronous receiver and transmitter (UART). The NEXTSat-1 has a lot of communications ports for performing science and technology missions. However, the top level system requirements for the NEXTSat-1 are mass and volume limitations. Normally, the communications for units shall be conducted by using point to point link which require more mass and volume to interconnect. Thus, our approach for the novel communications link in the NEXTSat-1 program is to use CAN and serializer and deserializer low voltage differential signal (SerDesLVDS) to meet the system requirements of mass and volume. The CAN Bus and SerDesLVDS were confirmed by using already defined communications link for our missions in the NEXTSat-1 program and the analysis results were reported in this study in view of data flow and size analysis.

• KIISE Transactions on Computing Practices
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• v.24 no.3
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• pp.129-137
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• 2018

NVMe(Non-Volatile Memory Express) SSD(Solid State Drive) is a high-performance storage that makes use of flash memory as a storage cell, PCIe as an interface and NVMe as a protocol on the interface. It supports multiple I/O queues which makes it feasible to process parallel-I/Os on multi-core environments and to provide higher bandwidth than SATA SSDs. Hence, NVMe SSD is considered as a next generation-storage for data-center and cloud computing system. However, in the virtualization system, the performance of NVMe SSD is not fully utilized due to the bottleneck of the software I/O stack. Especially, when it uses I/O stack of the hypervisor or the host operating system like Xen and KVM, I/O performance degrades seriously due to doubled-I/O stack between host and virtual machine. In this paper, we propose a new I/O engine, called Direct-AIO (Direct-Asynchronous I/O) engine, that can access NVMe SSD directly for I/O performance improvements on QEMU emulator. We develop our proposed I/O engine and analyze I/O performance differences between the existed I/O engine and Direct-AIO engine.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of Communications and Networks
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• v.7 no.2
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• pp.144-156
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• 2005

Video streaming over wireless networks is challenging due to node mobility and high channel error rate. In this paper, we propose a multi-source video streaming (MUVIS) system to support high quality video streaming service over IEEE 802.1l-based wireless networks. We begin by collocating a streaming proxy with the wireless access point to help leverage both the media server and peers in the WLAN. By tracking the peer mobility patterns and performing content discovery among peers, we construct a multi-source sender group and stream video using a rate-distortion optimized scheme. We formulate such a multi-source streaming scenario as a combinatorial packet scheduling problem and introduce the concept of asynchronous clocks to decouple the problem into three steps. First, we decide the membership of the multisource sender group based on the mobility pattern tracking, available video content in each peer and the bandwidth each peer allocates to the multi-source streaming service. Then, we select one sender from the sender group in each optimization instance using asynchronous clocks. Finally, we apply the point-to-point rate-distortion optimization framework between the selected sender-receiver pair. In addition, we implement two different caching strategies, simple caching simple fetching (SCSF) and distortion minimized smart caching (DMSC), in the proxy to investigate the effect of caching on the streaming performance. To design more realistic simulation models, we use the empirical results from corporate wireless networks to generate node mobility. Simulation results show that our proposed multi-source streaming scheme has better performance than the traditional server-only streaming scheme and that proxy-based caching can potentially improve video streaming performance.

• Journal of the Korea Society of Computer and Information
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• v.17 no.3
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• pp.41-50
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• 2012

In the monitoring system based on web service application, it is faced with the problems like code reproduction, difficult scalability and error recovery derived from the frequent change of data structure. So we propose a technique of monitoring system by DTD(Document Type Definition) automatic generation. This technique is to use dynamic server-side script to cope with the change of sensor data structure, generate the DTD dynamically. An it also adapt the AJAX(Asynchronous JavaScript and XML) for XML data parsing, it can support mass data transmission and exception processing for data loss and damage. This technique shows the result of recovery time is decreased about 44.8ms in case of temporary data failure by comparing to the conventional XML method.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of IKEEE
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• v.16 no.2
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• pp.86-94
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• 2012

Synchronization MAC Protocol such as S-MAC and T-MAC utilize duty cycling technique which peroidically operate wake-up and sleep state for reducing energy consumption. But synchronization MAC showed low energy efficiency because of additional control packets. For better energy consumption, Asychronization MAC protocols are suggested. For example, B-MAC, and X-MAC protocol adopt Low Power Listening (LPL) technique with CSMA algorithm. All nodes in these protocols joining a network with independent duty cycle schedules without additional synchronization control packets. For this reason, asynchronous MAC protocol improve energy efficiency. In this study, a low-power MAC protocol which is based on X-MAC protocol for wireless sensor network is proposed for better energy efficiency. For this protocol, we suggest preamble numbering, and virtual-synchronization technique between sender and receive node. Using TelosB mote for evaluate energy efficiency.