• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• International Journal of Contents
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• v.7 no.4
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• pp.30-34
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• 2011

A Leader is a Coordinator that supports a set of processes to cooperate a given task. This concept is used in several domains such as distributed systems, parallelism and cooperative support for cooperative work. In completely asynchronous systems, there is no solution for the election problem satisfying both of safety and liveness properties in asynchronous distributed systems. Therefore, to solve the election problem in those systems, one property should be weaker than the other property. If an election algorithm strengthens the safety property in sacrifice of liveness property, it would not nearly progress. But on the contrary, an election algorithm strengthening the liveness property in sacrifice of the safety property would have the high probability of violating the safety property. In this paper, we presents a safety strengthened Leader Election protocol with an unreliable failure detector and analyses it in terms of safety and liveness properties in asynchronous distributed systems.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.4
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• pp.405-412
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• 2013

This paper includes new protection concepts and practices to avoid mechanical damage of three-phase transformer by asynchronous operation of synchronous generator. this failure is often caused just after synchronous generator was connected to the grid because of a malfunction of the controller or misconnections of the synchronous devices. The results of the studies on the analyzing the phenomenon of asynchronous operation experienced in Korea and rapidly detecting asynchronous state are descrived.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.109-116
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• 2008

Model matching problem of asynchronous sequential machines is addressed in this paper. The main topic is to design a corrective controller such that the closed-loop behavior of the asynchronous sequential machine can follow a given model, i.e., their models can be "matched" in stable states. In particular, we assume that the considered asynchronous machine suffers from the presence of an input disturbance that can cause undesirable state transitions. The proposed controller can realize both model matching and elimination of the adverse effect of the input disturbance. Necessary and sufficient condition for the existence of a corrective controller that solves model matching problem is presented. Whenever controller exists, algorithms for their design are outlined and demonstrated in a case study.

• Journal of the Korea Society for Simulation
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• v.10 no.1
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• pp.25-34
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• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.414-416
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• 2000

We investigate potential advantages and problems when a superscalar processor is designed and implemented using asynchronous design methods. Conventional techniques of superscalar processing are applied and data dependent adder is considered as an asynchronous component. Intensive simulations on SPEC INT95 benchmark suites are made for the purpose of performance comparison between a synchronous and an asynchronous superscalar processor, respectively. The simulation results show about 5% speedup with asynchronous design methods in the sense of Issue Rate.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5449-5464
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• 2018

Recent works have validated the possibility of reducing the energy consumption in wireless heterogeneous networks, achieved by switching on/off some base stations (BSs) dynamically. In this paper, to realize energy conservation, the discrete time Markov Decision Process (DTMDP) is developed to match up the BS switching operations with the traffic load variations. Then, an asynchronous decision-making algorithm, which is based on the Bellman equation and the on/off priorities of the BSs, is firstly put forward and proved to be optimal in this paper. Through reducing the state and action space during one decision, the proposed asynchronous algorithm can avoid the "curse of dimensionality" occurred in DTMDP frequently. Finally, numerical simulations are conducted to validate the effectiveness and advantages of the proposed asynchronous on/off strategies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.891-901
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• 2003

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.