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http://dx.doi.org/10.3745/KIPSTA.2002.9A.3.351

Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis  

Kim, Eui-Seok (Gwangju Institute of Science and Technology)
Lee, Jeong-Gun ( Dept.of Information Electronics Commerce, Wonkwang University)
Lee, Dong-Ik ( Dept.of Information Electronics Commerce, Wonkwang University)
Publication Information
The KIPS Transactions:PartA / v.9A, no.3, 2002 , pp. 351-362 More about this Journal
Abstract
Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.
Keywords
Signal Transition Graph; Asynchronous Logic Synthesis; Control-Data Flow Graph; Automatic Derivation;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 T. A. Chu, 'Synthesis of self-timed VLSI circuits from graph-theoretic specifications,' Ph.D.Dissertation, MIT, Jun., 1987
2 J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, 'Petrify : A tool manipulating concurrent specifications and synthesis of asynchronous controllers,' IEICE Trans. Inf. & Syst., Vol.E.80-D, No.3, pp.315-325, Mar., 1997
3 E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton and A. Sangiovanni-Vincentelli, 'SIS : A System for Sequential Circuit Synthesis,' May, 1992
4 E. Kim, J.-G.Lee and D.-I.Lee, 'Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG,' In Proceedings of Advanced Research in VLSI 2001, pp.2-15, 2001   DOI
5 김의석, 이정근, 이동익, '프로세서 중심방식에 기반한 비동기식 유한상태기의 자동생성을 통한 분산 비동기식 제어부의 유도', 정보과학회논문지 : 시스템 및 이론, 제28권 제7.8호, 2001   과학기술학회마을
6 T. Murata, 'Petri Nets : Properties, Analysis and Applications,' Proceedings of the IEEE, Vol.77, No.4, pp.541-580, 1989   DOI   ScienceOn
7 S. Jung and C. J. Myers, 'Direct Synthesis of Timed Asynchronous Circuits,' IEEE International Conference on Computer Aided Design (ICCAD), pp.332-337, Nov., 1999   DOI
8 J. Cortadella and R. M. Badia, 'An Asynchronous Architecture Model for Behavioral Synthesis,' In Proceedings of European Conference on Design Automation, Mar., pp.307-311, 1992
9 I. Blunno and L. Lavagno, 'Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL,' In Proceedings of Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, Apr., pp.84-92, 2000   DOI
10 A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen and A. Yakovlev, 'Basic Gate Implementation of Speed-Independent Circuits,' ACM/IEEE Design Automation Conference, pp.55-62, Jun., 1994   DOI
11 J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, 'Petrify : a tool for manipulating concurrent specifications and synthesis of asynchronous controllers,' IEICE Transactions of Information and Systems, Vol.E80-D, No.3, pp.315-325, 1997
12 S. Hauck, 'Asynchronous Design Methodologies : an Overview,' Proceedings of the IEEE, Vol.83, No.1, pp.69-93, 1995   DOI   ScienceOn