• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.27-33
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• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.

• Communications of the Korean Mathematical Society
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• v.18 no.1
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• pp.159-168
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• 2003

In this paper we discuss the Construction Of 3 new extension field of characteristic odd and analyze the complexity of arithmetic operations over such a field. Also we show that it is suitable for Elliptic Curve Cryptosystems(ECC) and Digital Signature Algorithm(DSA, 〔7〕) as an underlying field. In particular, our digital signature scheme is at least twice as efficient as DSA.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.8 no.12
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• pp.127-138
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• 1985

There are several methods which have been presented up to now in solving the simultaneous linear equations by computer. They are Gaussian Elimination Method, Gauss-Jordan Method, Inverse matrix Method and Gauss-Seidel iterative Method. This paper is not only discussed in their mechanisms compared with their algorithms, depicted flow charts, but also calculated the numbers of arithmetic operations and comparisons in order to criticize their availability. Inverse Matrix Method among em is founded out the smallest in the number of arithmetic operation, but is not the shortest operation time. This paper also indicates the many problems in using these methods and propose the new method which is able to applicate to even small or middle size computers.

• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.101-108
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• 2017

As the quantum gate matrix is a $r^{n+1}{\times}r^{n+1}$ dimension when the radix is r, the number of control state vectors is n, and the number of target state vectors is one, the matrix dimension with increasing n is exponentially increasing. If the number of control state vectors is $2^n$, then the number of $2^n-1$ unit matrix operations preserves the output from the input, and only one can be performed the unitary operation to the target state vector. Therefore, this paper proposes a new method of function embedding that can replace $2^n-1$ times of unit matrix operations with deterministic contribution to matrix dimension by arithmetic power switch of the unitary gate. The proposed function embedding method uses a binary literal switch with a multivalued threshold, so that a general purpose hybrid MCU gate can be realized in a $r{\times}r$ unitary matrix.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1079-1085
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• 2013

Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple $2^M$ decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.

• Journal of the Korea Society of Computer and Information
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• v.13 no.2
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• pp.193-201
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• 2008

Using Network Coding in P2P systems yields great benefits, e.g., reduced download delay. The core notion of Network Coding is to allow encoding and decoding at intermediate nodes, which are prohibited in the traditional networking. However, improper implementation of Network Coding may reduce the overall performance of P2P systems. Network Coding cannot work with general arithmetic operations, since its arithmetic is over a Finite Field and the use of an efficient Finite Field arithmetic algorithm is the key to the performance of Network Coding. Also there are other important performance parameters in Network Coding such as Field size. In this paper we study how those factors influence the performance of Network Coding based systems. A set of experiments shows that overall performance of Network Coding can vary 2-5 times by those factors and we argue that when developing a network system using Network Coding those performance parameters must be carefully chosen.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.689-695
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• 2010

The effect of the code conversion process of Korean script (Hangul), also known as words for numbers, was investigated using event-related potentials (ERPs) during mental arithmetic operations. Study subjects were asked to determine whether the arithmetic results of a given target stimuli were correctly matched. Visual inspection and statistics of mean ERPs showed stimulus type-dependent processing rather than task-dependent processing. Results of addition and multiplication tasks revealed that the overall temporal profiles of the Arabic numerals were similar to the Hangul words for numbers. The only exception to this observation was a delayed positive-slope peak occurring around 300 ms, which was likely related to the encoding process of Hangul words for numbers to Arabic-digits, defined as a 'transcoding-related potential.' Source analysis confirmed that the topography of different waveforms for the two conditions was attributed to a single dipole located in the left temporo-parietal area; this area is known to be involved in Hangul words for number processing. These results suggest that the initial processing for encoding words for numbers was followed by arithmetic operations without direct access of internal number representation. Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society.