• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Research in Mathematical Education
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• v.18 no.1
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• pp.31-40
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• 2014

Working with dynamic visual representations can help students-with-computer discover new mathematical ideas. Students translate among multiple representations as a strategy to investigate non-routine problems to explore possible solutions in mathematics classrooms. In this paper, we use the area models as new representations for our secondary students to investigate three problems related to the average speed of a particle. Students show their ideas in the process of investigating arithmetic mean, harmonic mean, and average speed through their created dynamic figures. These figures really utilize dynamic geometry software.

• Journal of the Korean Mathematical Society
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• v.61 no.1
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• pp.161-181
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• 2024

We describe the moduli space of Higgs pairs on an irreducible nodal curve of arithmetic genus one and its geometric structures in terms of the Hitchin map and a flat degeneration of the moduli space of Higgs bundles on an elliptic curve.

• Bulletin of the Korean Mathematical Society
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• v.56 no.5
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• pp.1219-1233
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• 2019

Let $E{\rightarrow}M$ be an arbitrary vector bundle of rank k over a Riemannian manifold M equipped with a fiber metric and a compatible connection $D^E$. R. Albuquerque constructed a general class of (two-weights) spherically symmetric metrics on E. In this paper, we give a characterization of locally symmetric spherically symmetric metrics on E in the case when $D^E$ is flat. We study also the Einstein property on E proving, among other results, that if $k{\geq}2$ and the base manifold is Einstein with positive constant scalar curvature, then there is a 1-parameter family of Einstein spherically symmetric metrics on E, which are not Ricci-flat.

• Journal of Educational Research in Mathematics
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• v.20 no.3
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• pp.275-292
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• 2010

In this study, we discussed the way to teach algebra earlier through investigating to research trends of Early Algebra and researching about nature of subject involving algebra. There is a strong view that arithmetic and algebra have analogous forms and that algebra is on extension to arithmetic. Nevertheless, it is also possible to present a perspective that the fundamental goal and role of symbols and letters are difference between arithmetic and algebra. And, we could recognize that geometry was starting point of algebra trough historical perspectives. To consider these, we extracted some of possible directions to approaches to teach algebra earlier. To access to teaching algebra earlier, following ways are possible. (1) To consider informal strategy of young children. (2) Arithmetic reasoning considered of the algebraic relation. (3) Starting to algebraic reasoning in the context of geometrical problem situation. (4) To present young students to tool of letters and formular.

• Journal of the Korean Mathematical Society
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• v.59 no.6
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• pp.1103-1137
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• 2022

Our motivation in this note is to find equal hyperharmonic numbers of different orders. In particular, we deal with the integerness property of the difference of hyperharmonic numbers. Inspired by finiteness results from arithmetic geometry, we see that, under some extra assumption, there are only finitely many pairs of orders for two hyperharmonic numbers of fixed indices to have a certain rational difference. Moreover, using analytic techniques, we get that almost all differences are not integers. On the contrary, we also obtain that there are infinitely many order values where the corresponding differences are integers.

• Smart Structures and Systems
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• v.26 no.3
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• pp.311-318
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• 2020

The goal of this study is to analytically and non-stochastically generate structural uncertainty behaviors of isotropic beams and laminated composite plates under plane stress conditions by using an interval finite element method. Uncertainty parameters of structural properties considering resistance and load effect are formulated by interval arithmetic and then linked to the finite element method. Under plane stress state, the isotropic cantilever beam is modeled and the laminated composite plate is cross-ply lay-up [0/90]. Triangular shape with a clamped-free boundary condition is given as geometry. Through uncertainties of both Young's modulus for resistance and applied forces for load effect, the change of structural maximum deflection and maximum von-Mises stress are analyzed. Numerical applications verify the effective generation of structural behavior uncertainties through the non-stochastic approach using interval arithmetic and immediately the feasibility of the present method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal for History of Mathematics
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• v.22 no.1
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• pp.41-52
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• 2009

Dutch mathematician Simon Stevin published De Thiende(The Tenth) in 1583. In that book Stevin suggested new numerical notation which could express all numbers. That new notation was decimal fraction system. In this article I will argue that Stevin invented new decimal fraction system with two main purposes. The explicit purpose was to invent a new system which could be used easily by practical mathematicians. The implicit purpose which cannot be found in De Thiende alone but in his other writings was to break the Aristotelian tradition which separated geometry and arithmetic which dealt continuous magnitude and discrete numbers respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.