• Journal of the Korean Vacuum Society
• /
• v.7 no.s1
• /
• pp.156-158
• /
• 1998

This paper describes the preparation of boron-doped polycrystalline diamond thin film whose electrical resitivity is lower than $10^{-1}\Omega$cm. The 1$\times$1$\textrm{mm}^2$ microelectrodes, its conducting line with 0.2mm wide and 0.5$\times$0.5$\textrm{mm}^2$ pads was patterned by reactive ion beam etching. A glucose microsensor based on diamond film microelectrode and pyramidal containment produced on silicon by anisotropic etching was developed. Its advantages are high sensitivity and high stability.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.2 s.95
• /
• pp.60-67
• /
• 1999

Micro-fabrication techniques such as lithography and LIGA processes usually require large investment and are suitable for mass production. Therefore, there is a need for a new micro-fabrication technique that is flexible and more cost effective. In this paper a novel, economical and flexible method of producing micro-pattern on silicon wafer is presented. This method relies on selective removal of mask by mechanical cutting. Then micro-pattern is produced by chemical etching. V-shaped grooved of about 3 ${\mu}m$ wide and 2 ${\mu}m$ deep has been made on ${SiO_2}m$ coated silicon wafer with this method. This method may be utilized for making microstructures in MEMS application at low cost.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.741-744
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.739-742
• /
• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• 한국신재생에너지학회:학술대회논문집
• /
• 2007.11a
• /
• pp.264-267
• /
• 2007

It is important to reduce optical losses from front surface reflection to improve the efficiency of crystalline silicon solar cells. Surface texturing by isotropic etching with acid solution based on HF and $HNO_3$ is one of the promising methods that can reduce surface reflectance. Anisotropic texturing with alkali solution is not suitable for multicrystalline silicon wafers because of its various grain orientations. In this paper, we textured multicrystalline silicon wafers by simple wet chemical etching using acid solution to reduce front surface reflectance. After that, surface morphology of textured wafer was observed by Scanning Electron Microscope(SEM) and Atomic Force Microscope(AFM), surface reflectance was measured in wavelength from 400nm to 1000nm. We obtained 29.29% surface reflectance by isotropic texturing with acid solution in wavelength from 400nm to 1000nm for fabrication of multicrystalline silicon solar cells.

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.7
• /
• pp.51-58
• /
• 2002

In this paper, the characteristics of silicon wafer surface which is textured by KOH anisotropic etching method and mechanical polishing are investigated from the viewpoint of stiction and friction. It was found that the characteristics of stiction and friction of each textured surface are dependent on the contact area characterized by surface parameters such as bearing length ratio and peak count. To find the mechanism of the variation of stiction and friction in textured surface, OTS SAM coated wafer was used. In this case, the variation of stiction and friction was diminished, Therefore, it is concluded that the reason of variation of stiction and friction on textured surface is mainly caused by capillary which in turn is affected by the surface topography

• Proceedings of the KIEE Conference
• /
• 1995.11a
• /
• pp.600-602
• /
• 1995

Using the $O_2$ RIE process, 20{\mu}m$-height polyimide microstructures are fabricated. In LIGA-like process, metal microstructure can be formed by the electroplating using these polyimide microstructures as a plating mould. Reactive ion Etching technique using oxygen gas is used for the patterning of polyimide. The etching rate of the polyimide is increased with increased pressure and RF power. The anisotropic vertical sidewall can be obtained at low pressure, but the etched surface state is not so good yet. "Micrograss", which is formed during the RIE and disturbs uniform electroplating, can be removed effectively by the wet itching of the chromium sacrificial layer. More studies about the improvement of an etched surface state and the removal of microsgrass are needed.

• New & Renewable Energy
• /
• v.2 no.2 s.6
• /
• pp.4-8
• /
• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient Reff lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국신재생에너지학회:학술대회논문집
• /
• 2007.06a
• /
• pp.295-298
• /
• 2007

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• Journal of the Korean institute of surface engineering
• /
• v.50 no.5
• /
• pp.315-321
• /
• 2017

Antireflective pyramid arrays can be readily obtained via anisotropic etching in alkaline solution (KOH, NaOH), which is widely used in crystalline-Si (c-Si) solar cells. The periodic inverted pyramid arrays show even lower light reflectivity because of their superior light-trapping characteristics. Since this inverted pyramidal structures are mostly achieved using very complex techniques such as photolithograpy and laser processes requiring extra costs, here, we demonstrate the Cu-nanoparticle assisted chemical etching processes to make the inverted pyramidal arrays without the need of photolithography. We have mainly controlled the concentration of $Cu(NO_3)_2$, HF, $H_2O_2$ and temperature as well as time factors that affecting the reaction. Optimal inverted pyramid structure was obtained through reaction parameters control. The reflectance of inverted pyramid arrays showed < 10% over 400 to 1100 nm wavelength range while showing 15~20% in random pyramid arrays.