• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.81-88
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• 2004

In this paper, a low power area efficient charge recycling predecoder (AE-CRPD) is proposed. The AE-CRPD is modified from the conventional charge recycling predecoder (CNV-CRPD). The AE-CRPD significantly reduces the area and power of the control circuits for the charge recycling operation. It saves 38% area and 8% power of the 2-to-4 CNV-CRPD. It also utilizes the property of the consecutive address increase in the memory. The AE-CRPDs are used for the frequently transited least significant bits and the conventional predecoders are used for the occasionally transited most significant bits. It saves 23% power of the 12-bit conventional predecoder.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.653-656
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• 2005

New charge-recycling structure and driving scheme for TFT-LCD source-driver IC application are proposed. The number of additional switches for the charge recycling is greatly reduced. An experimental prototype 6-bit source driver with five-level seven-phase charge recycling implemented in a $0.35-{\mu}m$ CMOS technology demonstrates that the quiescent current is only 3.1 mA, dynamic power saving is 75 %, and the settling time, which includes the charge-recycling and data driving, is within 25 $25{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.821-827
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• 2001

A new low power charge-recycling ROM architecture is proposed. The charge-recycling ROM uses charge-recycling method in bit lines of ROM to save the power consumption. About 90% of the total power used in the ROM is consumed in bit lines. With the proposed method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amplifiers detect infinitely small voltage difference. However, the real sense amplifiers cannot sense very small voltage difference. Therefore, reduction of power consumption is limited. The simulation results show that the charge-recycling ROM only consumes 13% ~ 78% of the conventional low power contact programming mask ROM.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.661-662
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• 2006

This paper introduces a CMOS clock driver that shows a high efficiency of electric power (lower power consumption) with the supply of lower voltage(VDD), by taking advantage of charge recycling technology. Comparing with the existing structure, this driver showed the improved maximum efficiency of electric power; 72% and 68%, with the supplied voltage of 1.8v and 1.2v, respectively. Since the output waveform shows the tri-state operating region, utilization is expected in the digital integrated circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.9
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• pp.801-807
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• 2008

Recently, CV, CN-CV and CNCV-W cable are used for HVDC transmission and distribution cable. However, XLPE which is used as insulation layer of power cable has thermosetting properties. It is very difficult to recycling. In this paper, we prepared HDPE/EVA film, which the blending ratio are 80:20, 70:30, 60:40, 50;50 respectively for the purpose of recycling. Main factor such as electric field distribution and its resistivity in insulation system affected on insulation performance and reliability for HVDC applications. Therefore, electric field distribution formed by space charge and characteristics of volume resistivity was currently investigated. We suggest the possibility of utilization for HVDC insulation layer from the results.

• Resources Recycling
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• v.12 no.5
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• pp.3-9
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• 2003

In order to prospect current recycling status in Korea, legislative system and policies relating to recycling, wastes generation and recycling rate were reviewed. Approximately 260,400 ton/day of wastes was generated in 2001. 48,400 ton/day of household waste and 212,000 ton/day of industrial waste. During the last ten years, waste management laws such as waste disposal law, recycling law and environment friendly industry law were prepared. In this article, concerning over waste generation and recycling, recycling law, Extended Producer Responsibility System and the problems and technological developments associated with recycling were summarized.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1088-1091
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• 2009

A boost converter with charge-recycling technique fabricated by $0.25{\mu}m$ CMOS BCD process can provide different supply voltages to drive series RGB LEDs in sequence for reducing the power consumption on the constant current generator. The proposed technique stores and restores extra energy to improve the efficiency, as well as enhances the reference tracking response. Experimental results show that the period of reference-tracking response can be improved. When the load current is 100mA, the periods of reference down-tracking and uptracking are smaller than $10{\mu}s$ and $20{\mu}s$, respectively. Experimental results demonstrate fast and efficient reference tracking performance is achieved.

• Journal of Korea Society of Waste Management
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• v.35 no.8
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• pp.785-798
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• 2018

Since the Framework Act on Resource Circulation was enacted in 2018, the government should establish a National Resource Circulation Master Plan every 10 years, which defines mid- to long-term policy goals and directions on the efficient use of resources, prevention of waste generation and recycling of waste. In addition, we must set mid- to long-term and stepwise targets for the final disposal rate, recycling rate (based on sorted recyclable materials and recycled products), and energy recovery rate of wastes, and relevant measures should be taken to achieve these targets. However, the current industrial waste (IW) statistics have limitations in setting these targets because the final disposal rate and recycling rate are calculated as the ratio of the recycling facility input to the IW generation. In this study, the material flow from the collection stage to the final disposal of industrial waste was analyzed based on the generation of 2016, and the actual recycling amount, actual incineration amount, final disposal amount and their rates were calculated. The effect on the recycling, incineration and final disposal rates was examined by changing the treatment method of nonhazardous wastes from the factory and construction and demolition wastes, which were put in landfills in 2016. In addition, the variation of the waste treatment charge was investigated according to the change of treatment methods. The results of this study are expected to be effectively used to establish the National Resource Circulation Master Plan and industrial waste management policy in the future in South Korea.

• Journal of information and communication convergence engineering
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• v.15 no.1
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• pp.62-71
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• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.