• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.225-231
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• 2010

In this paper, we investigate the channel thermal noise in nanoscale MOSFETs. Simple analytical model of thermal noise factor in nanoscale MOSFETs is presented and it is verified with accurately measured noise data. The noise factor is expressed in terms of the channel conductance and the electric field in the gradual channel region. The proposed noise model can predict the channel thermal noise behavior in all operating bias regions from the long-channel to nanoscale MOSFETs. From the measurement results, we observed that the thermal noise model for the long-channel MOSFETs does not always underestimate the short-channel thermal noise.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.316-321
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• 2005

A new HBT current source model and the corresponding direct parameter extraction methods are presented. Exact analytical expressions for the current source model parameters are derived. This method is applied to scalable modeling of HBT, Some techniques to reduce redundancy of the parameters are introduced. The model based on this method can accurately predict the measured data for the change of ambient temperature, size, and bias.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.50-53
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• 2001

In this study, gate leakage current mechanism has been analyzed for GaAs MESFET with different temperatures ranging from 27$^{\circ}C$ to 300$^{\circ}C$ . It is expected that the thermionic and field emission at the MS contact will dominate the current flow. Thermal cycle is applied to test the reliability of the device. From the results, it is proved that thermal stress gradually increases the gate leakage current at the same bias conditions and leads to the breakdown and failure mechanism which is critical in the field equipment. Finally the gate contact under the repeated thermal shock has been tested to check the quality of Schottky barrier and the current will be expressed in the analytical from to associate with the electrical characteristics of the device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.118-121
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• 1995

Fabrication and a new analytical expression for the capacitance characteristics of hydrogenerated amorphous silicon thin film transistors(a-Si:H TFTs) is presented and experimentally verified. The results show that the experimental capacitance characteristics are easily measeured. Measured transfer and DC output characteristic curves of a-Si:H TFT are similar to those of the standard MOSFET-IC. The capacitances on bias voltages are in good agreement with experimental data. This capacitance characteristics is suitable for incorporation into a circuit simulator and can be used for computer-aided design of a-Si thin film transistor integrated circuits.

• Asian-Australasian Journal of Animal Sciences
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• v.10 no.5
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• pp.510-513
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• 1997

This study examined the effects of ignoring inbreeding depression on (co)variance components for weaning weight through the use of Monte Carlo simulation. Weaning weight is of particular interest as a trait for which additive direct and maternal genetic components exist and there then is the potential for a direct-maternal genetic covariance. Ignoring inbreeding depression in the analytical model (.8 kg reduction of phenotypic value per 1% inbreeding) led to biased estimates of all genetic (co) variance components, all estimates being larger than the true values of the parameters. In particular, a negative bias in the direct-maternal genetic covariance was observed in analyses that ignored inbreeding depression. A small spurious sire-by-year interaction variance was also observed.

• International Journal of Fluid Machinery and Systems
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• v.10 no.3
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• pp.197-208
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• 2017

When Francis turbines operate at partial load, residual swirl in the draft tube causes low-frequency pulsation of pressure and power output. Scale effects and system response may bias the prediction of prototype behavior based on laboratory tests, but could be overcome by means of a 1D analytical model. This paper deals with the two most important features of such a model, the compliance and the source of excitation. In a distributed-parameter version, compliance should be represented as an exponential function of local pressure. Lack of similarity due to different Froude number can thus be compensated. The normally unknown gas content in the vortex cavity has significant influence on the pulsation, and should therefore be measured and considered as a test parameter.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.193-196
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• 1987

We reported that hot electron phenomena in submicron nMOSFET by Monte Carlo method. In order to predict the influence of the hot electron effects on the device reliability, either simple analytical model or a complete two dimensional numerical simulation has been adopted. Results of numerical simulation, based on the static mobility model, may be inaccurate when gate length of MOSFET is scaled down to less than 1um. Most of device simulation packages utilize the static nobility model. Monte Carlo method based on stochastic analysis of carrier movement may be a powerful tool to characterize hot electrons. In this work, energy and velocity distribution of carriers were obtained to predict the relative degree of short channel effects for different device parameters. Our analysis shows a few interesting results when $V_{ds}$ is 5 volt, average electron energy does not increase with gate bias as evidenced by substrate current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.139-144
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• 2013

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.445-448
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• 1999

In this Paper, we present simple physical model of the Capacitance characteristics for GaAs MESFET\`s in wide temperatures. In this model, gate-source and gate-drain capacitances are represented by analytical expressions which are classified into three different regions for bias voltage. This model contained the temperature dependent variable that is the built-in voltage and the depletion width. Using the equations obtained in this work a submicron gate length MESFET has simulated and theoretical result are in good agreement with the experimental measurement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.895-900
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• 2000

In this paper, C-V characteristics based on the structure of GaAs MESFET’s has been proposed with wide range of applied voltages and temperatures. Small signal capacitance; gate-source and gate-drain capacitances are represented by analytical expressions which are classified into two different regions; linear and saturation regions with bias voltages. The expression contains two variables; the built-in voltage( $V_{vi}$ )and the depletion width(W). Submicron gate length MESFETs has been selected to prove the validity of the theoretical perdiction and shows good agreement with the experimental data over the wide range of applied voltages.