• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.829-832
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• 2007

A high-speed and accurate analog buffer is proposed for mobile display using LTPS TFTs. The proposed analog buffer is common source type with sampling and negative feedback mode. Therefore, driving speed of the proposed buffer is faster than previously reported one. In addition, the accuracy is very high because of high negative feedback gain. The simulation results show that maximum mischarging voltage of the proposed buffer is 8mV and previously reported one is 37mV. And Power consumption of the proposed buffer is $43.1{\mu}W$, which is 73% of previously reported one.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.394-399
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• 1987

It is necessary for the speech samples to be stored in memory buffer before speech analyzers without a real time processor process them. In this paper, we propose an algorithm that uses the buffer efficiently, when the analog speech signal is converted to the digital samples by the analog to digital converter. In order to implement this method in real time, the buffer is divided into the starting buffer and the remaining buffer. Until a voiced speech is found, the converted samples are sequentially stored in the starting buffer, and then the buffer is shifted. When a voiced speech is found, the next samples are sequentally recorded in the remaining buffer.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1287-1290
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• 2006

A high speed analog buffer using polycrystalline silicon (poly-Si) thin film transistors (TFT) is proposed for 2.2-inch quarter video graphic adapter (qVGA) TFT-LCD panel. Simulation results show that the settling time of the proposed circuit is $10{\mu}sec$ in 2.2-inch qVGA and the power consumption of proposed analog buffer is $25{\mu}W$.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.696-699
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• 2008

A 10-bit source driver using low temperature poly-silicon(LTPS) TFTs is developed. To reduce the DAC area, the DAC structure including two 5-bit resistor-string DACs and analog buffer, which has analog adder is proposed. The source driver is fabricated using LTPS process and its one channel area is $3,200{\mu}m\;{\times}\;260{\mu}m$. The simulated INL and DNL of output voltages are less than 3 LSB and 1 LSB, respectively.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.999-1002
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• 2004

We propose and simulate a new integrated DAC analog buffer composed of only p-type poly-Si TFTs in AMLCD and AMOLED. Proposed circuit employs a voltage level shifter which $V_{OUT}$ has a linear functional relation to $V_{IN}$. The proposed scheme enables to allow a constant $V_{GS}$ of buffer transistor so that the charging speed of pixel data address is improved.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.