• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.3
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• pp.35-42
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• 2021

The research of amplifier have been actively conducted to replace the Traveling Wave Tube Amplifier (TWTA) in the mmWave. For Solid State Power Amplifiers (SSPA), which combine semiconductor-type devices to obtain high output, Low-loss, high-efficiency combination techniques are required to meet the required output as the output of a single relatively low device is relatively low. In this paper, we design and produce an 8-way waveguide combiner and a reflective loss of more than 20dB and a binding efficiency of 85% or more were identified. Field analysis calculates the critical power inside the combiner. It secured stable Power Ratings and built-in coupler for power monitoring to achieve miniaturization and light weight.

• Journal of IKEEE
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• v.26 no.3
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• pp.456-461
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• 2022

In this paper, a two-stage single-ended power amplifier (PA) with broadband gain characteristics was presented by utilizing a radio frequency (RF) transformer (TF), which is essential for a differential amplifier. The bandwidth of a PA can be improved by designing TF to have broadband characteristics and then applying it to the inter-stage matching network (IMN) of a PA. For broadband gain characteristics while maintaining the performance and area of the existing PA, an IMN was implemented on an monolithic microwave integrated circuit (MMIC) and a multi-layer printed circuit board (PCB), and the simulation results were compared. As a result of simulating the PA module designed using InGaP/GaAs HBT model, it has been confirmed that the PA employing the proposed design method has an improved fractional bandwidth of 19.8% at a center frequency of 3.3GHz, while the conventional PA showed that of 11.2%.

• The Journal of the Acoustical Society of Korea
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• v.40 no.3
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• pp.247-253
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• 2021

Directional ultrasonic speakers that are used to hear sound only in a specific area have been continuously researched on various improvements in terms of sound quality and cost compared to general speakers. In this paper, we propose a DSP based hybrid-type ultrasonic speaker that can be heard at the same time as a general speaker in order to compensate for the sound in the low-band range, considering that it is difficult to hear the low-band sound below 500 Hz due to the sensor characteristics of the ultrasonic speaker. In the case of the system that is implemented by simply connecting a general speaker and an ultrasonic speaker, there are issues of high cost and difficulties of control as two amplifiers are used to playback ultrasonic and general sound sources. In addition, sound quality deteriorates due to the difference in playback time between ultrasonic and general sound sources. In order to improve issues of cost, control and sound quality, we developed hybrid-type ultrasonic speaker with a DSP based amplifier that can simultaneously playback by synchronizing the general sound source with the regenerated ultrasonic sound source, in addition to implement the existing CODEC functions such as Dynamic Range Control (DRC) and Equalizer (EQ).

• Journal of IKEEE
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• v.26 no.4
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• pp.537-544
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• 2022

This paper analyzes the occurrence and cause of bond wires fusing used in the manufacture of pulsed high power amplifiers. Recently GaN HEMT has been spotlight in the fields of electronic warfare, radar, base station and satellite communication. In order to produce the maximum output power, which is the main performance of the high-power amplifier, optimal impedance matching is required. And the material, diameter and number of bond wires must be determined in consideration of not only the rated current but also the heat generated by the transient current. In particular, it was confirmed that compound semiconductor with a wide energy band gap such as GaN trigger fusing of the bond wire due to an increase in thermal resistance when the design efficiency is low or the heat dissipation is insufficient. This data has been simulated for exothermic conditions, and it is expected to be used as a reference for applications using GaN devices as verified through IR microscope.

• Korean Journal of Optics and Photonics
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• v.33 no.3
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• pp.99-105
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• 2022

We have evaluated the performance of an all-optical automatic gain-controlled (AGC) erbium-doped fiber amplifier (EDFA) to suppress the optical signal fluctuation induced by atmospheric turbulence in terrestrial free-space optical communication systems. In our measurements, the input power into the EDFA was set to be -30 dBm and -10 dBm to operate the amplifier in the small-signal and saturation regions, respectively. The fluctuations in the optical signal were emulated with an acousto-optic modulator driven with a sinusoidal voltage. From the measured results, we have found that an all-optical AGC EDFA could suppress the optical signal fluctuation effectively, as long as the EDFA operated in the small-signal region with a high feedback amplified spontaneous emission (ASE) power.

• ETRI Journal
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• v.45 no.1
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.149-154
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• 2022

Due to high power capabilities and high linearity of GaN devices, GaN Low-Noise Amplifiers (LNAs) without a limiter can be implemented in order to improve noise figure and reduce chip area in radar receivers. In this paper, a GaN LNA is presented for Ka-band radar receivers. The designed LNA was realized in a 150-nm GaN HEMT process and measurement results show that the voltage gain of >23 dB and the noise figure of <6.5 dB including packaging loss in the target frequency range. Under the high-power stress test, measured gain and noise figure of the GaN LNA is degraded after the first stress test, but no more degradation is observed under multiple stress tests. Through post-stress noise and s-parameter measurements, we verified that the GaN LNA is resilient to pulsed input power of ~40 dBm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1055-1063
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• 2013

Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this LNA is $0.202mm^2$, including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7~8 dB over 1.5~13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.