• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.06a
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• pp.243-246
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• 1997

A new technique for low temperature crystallization of amorphous silicon, called field aided lateral crystallization(FALC) was attempted. To demonstrate the concept of FALC, thin layer of nickel(30${\AA}$) was deposited on top of amorphous silicon film and the electric field was applied during the crystallization. The effects of electric field on the crystallization behavior of amorphous silicon film were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.77-80
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• 2001

Crystallographic and magnetic characteristics of CoCr-based magnetic thin film for perpendicular magnetic recording media were influenced on preparing conditions. In these, there is that substrate temperature was parameter that increases perpendicular coercivity of CoCrTa magnetic layer using recording layer. While preparation of CoCr-based doublelayer, by optimizing substrate temperature, we expect to increase perpendicular anisotropy of CoCr magnetic layer and prepare ferromagnetic recording layer with a good quality by epitaxial growth. CoCrTa/Si doublelayer showed a good dispersion angle of c-axis orientation $\Delta\theta_{50}$ caused by inserting amorphous Si underlayer which prepared at underlayer substrate temperature 250C. Perpendicular coercivity was constant, in-plane coercivity was controlled a low value about 200Oe. This result implied that Si underlayer could restrain growth of initial layer of CoCrTa thin film, which showed bad magnetic properties effectively without participating magnetization patterns of magnetic layer. In case of CoCrTa/Si that prepared with ultra thin underlayer, crystalline orientation of CoCrTa was improved rather underlayer thickness 1nm, it was expected that amorphous Si layer played a important role in not only underlayer but also seed layer.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.127-130
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• 1989

This paper reports the theoretical model and the experimental results regarding to the electrical conductivity of hydrogenated amorphous silicon (a-Si:H). The total effective conductance of a-Si:H with a planar structure has been considered as the sum of the conductance of an adsorbate-induced layer, a surface-interface layer, a bulk layer, and a substrate-interface layer. In order to investigate the effects of space charge layers in a-Si:H on the conductivity, the thickness dependence of the conductivity is characterized and the conductivities measured at the upper electrodes deposited on a-Si:H are compared with those measured at the lower electrodes deposited on the glass substrate. From our analysis, the bulk conductivity and the thickness of the space charge layer in a-Si:H are characterized quantitatively.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.465-465
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• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• Journal of Information Display
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• v.10 no.3
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• pp.117-120
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• 2009

A new crystallization method for amorphous silicon, called selective area heating (SAH), was proposed. The purpose of SAH is to improve the reliability of amorphous silicon films with extremely low thermal budgets to the glass substrate. The crystallization time shortened from that of the conventional solid-phase crystallization method. An isolated thin heater for SAH was fabricated on a quartz substrate with a Pt layer. To investigate the crystalline properties, Raman scattering spectra were used. The crystalline transverse optic phonon peak was at about 519 $cm^{-1}$, which shows that the films were crystallized. The effect of the crystallization time on the varying thickness of the $SiO_2$ films was investigated. The crystallization area in the 400nm-thick $SiO_2$ film was larger than those of the $SiO_2$ films with other thicknesses after SAH at 16 W for 2 min. The results show that a $SiO_2$ capping layer acts as storage layer for thermal energy. SAH is thus suggested as a new crystallization method for large-area electronic device applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.322.1-322.1
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• 2014

Many research groups have studied tandem or multi-junction cells to overcome this low efficiency and degradation. In multi-junction cells, band-gap engineering of each absorb layer is needed to absorb the light at various wavelengths efficiently. Various absorption layers can be formed using multi-junctions, such as hydrogenated amorphous silicon carbide (a-SiC:H), amorphous silicon germanium (a-SiGe:H) and microcrystalline silicon (${\mu}c$-Si:H), etc. Among them, ${\mu}c$-Si:H is the bottom absorber material because it has a low band-gap and does not exhibit light-induced degradation like amorphous silicon. Nevertheless, ${\mu}c$-Si:H requires a much thicker material (>2 mm) to absorb sufficient light due to its smaller light absorption coefficient, highlighting the need for a high growth rate for productivity. ${\mu}c$-SiGe:H has a much higher absorption coefficient than ${\mu}c$-Si:H at the low energy wavelength, meaning that the thickness of the absorption layer can be decreased to less than half that of ${\mu}c$-Si:H. ${\mu}c$-SiGe:H films were prepared using 40 MHz very high frequency PECVD method at 1 Torr. SiH4 and GeH4 were used as a reactive gas and H2 was used as a dilution gas. In this study, the ${\mu}c$-SiGe:H layer for triple solar cells applications was performed to optimize the film properties.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.6-12
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• 2013

Aerosol deposition(AD) coating that enable fabricate films at low temperature have begun to be widely researched for the integration of ceramics as well to realize high-speed deposition rates. For application of ceramic thick film by AD to display and electronic ceramic industry, fabrication of dense structure with a no cracking is required. In this study, to fabricate dense ceramic thick film, the effect of crystal phase of starting powder was investigated. For this study, amorphous and crystalline $SiO_2$ powders were used as starting powders. Two types of $SiO_2$ powders were deposited on glass substrate by AD. In the case of amorphous $SiO_2$ powder, the deposited films had extremely incompact and opaque layer, irrespective of particle size. In contrast to amorphous powder, in the case of crystalline powder, porous structure layer and dense microstructure with no cracking layer were fabricated depending on the particle size. The optimized starting powder size for dense coating layer was $1{\sim}2{\mu}m$. The transmittance of film reached a maximum of 76% at 800 nm.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1344-1347
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• 2007

We have fabricated bottom gate TFTs with active layers of amorphous/microcrystalline Si double layers (DL). Dynamic electric stresses were applied to DL TFTs and a-Si TFTs to compare their degradation characteristics. The DL TFTs were more stable under dynamic stresses than a-Si TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.