• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.2215_2216
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• 2009

As a driving method of AC PDP, address display separated (ADS) scheme has been widely used. In ADS method, a picture of one frame is divided into eight subfields. In this paper, the effect of sustain voltage stress have been studied with several parameters. The experimental results show that sustain pulses in the previous subfield work as the stress to address discharge in the current subfield. It is also shown that as the voltage of the sustain period in the previous subfield increases, the address time lag in the current subfield decrease slightly.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.105-108
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• 2003

A new high speed addressing method is proposed to reduce the addressing time below lus per line in AC PDP. In this method, the priming discharge is used to achieve a high speed addressing without adding an auxiliary electrode. Two different types of priming discharges were studied to achieve a high speed addressing and also reduce the inherent light output caused by the priming discharge in order to improve the contrast ratio characteristics. In the panel experiment, the addressing was successfully done with a lus address pulse width in the new method and the better contrast ratio was achieved in the Y-A priming rather than the Y-X priming case even though the reduction of the address period was smaller than that of the Y-X priming due to the extra address time for the priming discharges.

• 전자공학회논문지
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• 제51권2호
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• pp.168-172
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• 2014

교류형 플라즈마 디스플레이에서 유지기간 중에 자기소거 방전을 발생시켜서 휘도효율을 향상시키기 위한 새로운 유지 구동방법이 제안된다. 일반적인 AC PDP에서 하나의 서브필드 시간은 초기화, 기입, 유지기간으로 나누어져 있다. 그 중 유지기간 동안에 2개의 상판 전극인 X와 Y 전극에 교대로 사각 유지파형이 인가되어 화상을 표시하기 위한 유지기간 중의 플라즈마 방전이 연속적으로 발생된다. 그러나 일반적인 구동방법에 있어서 하판의 A전극에는 기입기간에서 종래의 구동방법에서는 셀을 선택할 때만 기입파형이 구동되고 유지기간 중에는 접지 상태로 놓여있으므로 유지 방전에 관여하지 않는다. 본 실험에서는 유지기간 중에 자기소거 방전을 발생시켜 휘도효율을 상승시키기 위하여 유지펄스의 뒷부분에서 음의 펄스를 A전극에 인가하였다. A전극의 음의 펄스는 주 유지방전이 발생된 후 셀 내부의 공간전하들을 벽전하로 전환시켜서 3전극의 전위가 접지 상태가 될 때 재 축적된 벽전하로 인하여 방전을 한번 더 유도시켰다. 그 결과, 유지기간 중 A 전극의 전압 높이에 따른 휘도 효율을 측정하였고 최적의 구동전압을 적용했을 때 휘도효율을 측정한 결과 종래와 비교해서 약 40 % 향상되었다.

• 건축역사연구
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• 제25권6호
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• pp.45-60
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• 2016

Sangnyang-mun(上樑文) is not only a memorial address for the ceremony of putting up the ridge beam, namely the sangnyang-ceremony(上樑式) but also the executional record of building construction. This paper aims at researching on the oldest five sangnyang-muns written for the constructions of palaces and government offices in Goryeo Dynasty, especially viewed in the architectural history. The results of that are as follows: First, it is supposed that sangnyang-mun originated in the ancient Chinese ceremonial songs for the celebration of building construction. Second, as compared against the former times, the sangnyang-muns in Goryeo Dynasty were written to the advanced establishing forms and literary patterns, so to speak, these were the more developed styles. Third, in the 12th century, sangnyang-mun was introduced from Chinese Song to Goryeo. To the late period of J oseon Dynasty, sangnyang-mun had been to write for the sangnyang-ceremony as necessary memorial address. Fourth, the writers of five sangnyang-muns in Goryeo Dynasty were the new civil ministers appointed by the soldier rulers. They wrote the contents of their sangnyang-muns, especially focused to the king's achievements. And in the yugwi-song(六衛頌), they recited six poems in which were complicated the world view and aesthetics of the time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.976-979
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control' writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm), To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and $0.5{\times}0.5mm^2$ area, respectively, This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolpution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• Transactions on Electrical and Electronic Materials
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• 제3권1호
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• pp.30-37
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control'writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm). To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and 0.5 $\times$ 0.5 mm$^2$area, respectively. This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• 전기학회논문지
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계합동학술대회 논문집
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• pp.149-152
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• 2002

If the ambient temperature rises for AC PDP, some of the discharge cells are turned off because of the misfiring during address period. Particularly, the misfiring of the 'last scan line is more serious than that of the first. In order to compensate the misfiring in such that case, different addressing voltage is applied at each cell such as progressively increasing pulse voltage instead of constant one. As a result, the addressing time and discharge charge of the last scan line have become similar to those of the first scan line and the phenomenon of misfiring has disappeared.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.170-173
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• 2003

The driving method is one of the most important factors of PDP, so various driving methods have been developed to improve the duality of PDP Nowadays, most of PDPs apply to ADS (Address and Display period Separated) driving method. In this paper, a new driving method that divides scan lines into multi-Blocks is suggested. The proposed driving method in this paper can drive 14 sub-fields per 1 TV field in SD panel, 16 sub-fields per 1 TV field in HD panel. And sufficient Address margin can be obtained.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권11호
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.