• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.967-970
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• 2003

A new adder-and-accumulator (A$^2$C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in $A^2$C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed $A^2$C has been verified by HSPICE simulations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.1
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• pp.15-22
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• 1974

A new ternary full adder using the current controlled negative-resistance circuit is described. The full adder is constructed from the modified-half-adder which was devised by making use of a negative resistance circuit. This full adder makes the number of its gates decrease and makes its own speed increase in comparison with the full adders which had been introduced previously. It is convenient to construct to the integrated circuit because transistor, SBD(Schottky Barrier Diode) and resistors were used as the circuit elements.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.167-170
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• 2000

This paper describes a novel multi-operand radix-2 signed-digit(SD) adder. The novel multi-operand addition algorithm can eliminate carry propagation chain by dividing the input operands into even place part and odd place part, and adding them each. The multi-operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary method of SD adder binary tree. A hardware model for proposed adder is shown which is implemented by the current-mode MOSFET circuit technology. Simulations have been made by SPICE in order to verify the function of the proposed circuit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.26-33
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• 1994

Optical adders using a modified signed-digit(MSD) number system have been proposed to restrict the carry propagation chain encountered in a conventional binary adder to two positions to the left. But, MSD number system must encode three different states to represent the three possible digits of MSD. In this paper, we propose the design of an optical adder based on 1-bit addition rules by using the method of symbolic substitution (SS). We show that this adder can use binary input which is used by a digital computer, as it is and be implemented by smaller system in size than MSD adder.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.11
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• pp.491-494
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• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korea Society of Computer and Information
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• v.15 no.10
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• pp.1-9
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• 2010

In this paper, we propose a methodology in which a power-delay product of a binary adder is optimized based on the heterogeneous adder architecture. We formulate the power-delay product of the heterogeneous adder by using integer linear programming(ILP). For the use of ILP optimization, we adopt a transformation technique in which the initial non-linear expression for the power-delay product is converted into linear expression. The experimental result shows the superiority of the suggested method compared to the cases in which only conventional adder is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.