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http://dx.doi.org/10.9708/jksci.2010.15.10.001

Power-Delay Product Optimization of Heterogeneous Adder Using Integer Linear Programming  

Kwak, Sang-Hoon (서울대학교 전기공학부)
Lee, Jeong-Gun (한림대학교 컴퓨터공학과)
Lee, Jeong-A (조선대학교 컴퓨터공학과)
Publication Information
Journal of the Korea Society of Computer and Information / v.15, no.10, 2010 , pp. 1-9 More about this Journal
Abstract
In this paper, we propose a methodology in which a power-delay product of a binary adder is optimized based on the heterogeneous adder architecture. We formulate the power-delay product of the heterogeneous adder by using integer linear programming(ILP). For the use of ILP optimization, we adopt a transformation technique in which the initial non-linear expression for the power-delay product is converted into linear expression. The experimental result shows the superiority of the suggested method compared to the cases in which only conventional adder is used.
Keywords
heterogeneous adder; power-delay product; integer linear programming;
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