• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1622-1631
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• 1997

A 3-stages Active Microstrip Phased Array Antenn(AMPAA) is implemented using Injection-Locking Coupled Oscillators(ILCO). The AMPAA is a beam scanning active antenna with capability of electrical scanning by frequency varation of ILCO. The synchronization of resonance frequencies in array elements is occured by ILCO, and the ILCO amplifies the injection signal and functions as a phase shifter. The microstrip ptch is operated as a radiation element. The unilateral amplifier is a mutual coupling element of AMPAA, eliminates the reverse locking signal and controls the locking bandwidth of ILCO. The possibility of Monolithic Microwave Integrated Circuits(MMIC) of T/R module is proposed by simplified and integrated fabrication process of AMPAA. The 0.75.$lambda_{0}$ is fixed for a mutual coupling space to wide the scanning angle and minimize the multi-mode. The AMPAA has beam scanning angle of 31.4.deg., HPBW(Half Power Beam Widths) of 26.deg., directive gain of 13.64dB and side lobe of -16.5dB were measured, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.8
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• pp.1566-1571
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• 2011

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

• Journal of IKEEE
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• v.11 no.3
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• pp.122-128
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• 2007

Sinusoidal voltage-controlled oscillators (VCOs) based on Colpitts and Hartley oscillators are presented. They consist of a LC parallel-tuned circuit connected in a negative-feedback loop with an OTA-R amplifier and two diode limiters, where the inductor is simulated one realized with temperature-stable linear operational transconductance amplifiers (OTAs) and a grounded capacitor. Prototype VCOs are built with discrete components. The Colpitts VCO exhibits less than 1% nonlinearity in its current-to-frequency transfer characteristic from 4.2 to 21.7 MHz and ${\pm}$95 ppm/$^{\circ}C$ temperature drift of frequency over 0 to $70^{\circ}C$. The total harmonic distortion (THD) is as low as 2.92% with a peak-to-peak amplitude of 0.7 V for a frequency-tuning range of 10.8-32 MHz. The Hartley VCO has the temperature drift and THD of two times higher than those of the Colpitts VCO.

• Journal of the Korean Institute of Telematics and Electronics
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• v.3 no.4
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• pp.16-24
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• 1966

The LASER Amplifier is treated in the manner of a Fabry-Perot Resonator with an active media, five layers are considered: air, reflector, active medium(ruby), reflector and air. One dimensional scalar wave equations are derived using the method of boundary value probrems in which it is assumed that incident coherent radiation falls normally on the surface wall. All equations are treated from the transient analysis point of view using the Laplace transform nethods, and are arranged steady state region as an amplifier and transient region as a self excited oscillator. Also some remarks are given on the design problem of LASER amplifier in connection with the transient terms involved.

• Journal of Advanced Navigation Technology
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• v.8 no.1
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• pp.57-65
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• 2004

In this paper, keeping pace with light weight, pocket-size, lower-price, we design VCO(Voltage Controlled Oscillator) X/Ku band for using at public RD(Radar Detector) to apply to controlled voltage on base in transistor which used as a oscillator, without using varactor diode in part of VCO tuner. As a result of simulation, we conclude VCO could be have 110 MHz by controlled voltage 4.25 V to 4.80 V and show its output 9.63 dBm at operating frequency, 11.46 GHz, and its phase noise -107.2 dBc at 1 MHz offset frequency. So it turned out suitable performance for commercial use.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.11
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• pp.536-543
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• 2003

In this paper, we describe a unique self oscillating and mixing (SOM) down-converter design using a modified defected ground structure (DGS). The proposed SOM converter is consisted of self-oscillator, which can produce negative resistance and select resonance frequency, RF matching circuit, and IF low pass filter. As the advantage of this SOM converter can mix LO and RF signals as well as inducing LO signal with only one active device. it is designed as a simple structure and the low cost. Also, there is easy advantage to be applied in RFIC/MMIC technology because it offers excellent phase noise performance in spite of using micro-strip structure. The LO signal for the proposed SOM converter is designed at 1㎓ and RF frequency was chosen to be 800MHz. The achieved conversion loss and phase noise performances of the implemented SOM converter are 15㏈ and -95dBc/Hz at 100KHz offset frequency respectively. The equivalent circuit parameters for DGS are extracted by using a three dimensional EM simulator and simple circuit analysis method.