• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1999년도 PROCEEDINGS OF 99 INTERNATIONAL CONFERENCE OF THE KACG AND 6TH KOREA·JAPAN EMG SYMPOSIUM (ELECTRONIC MATERIALS GROWTH SYMPOSIUM), HANYANG UNIVERSITY, SEOUL, 06월 09일 JUNE 1999
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• pp.271-284
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• 1999

As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides (SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single-crystalline 4H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 4H-SiC homoepitaxial layers using a SiC-uncoated graphite susceptor that utilized Mo-plates was obtained. The CVD growth was performed in an RF-induction heated atmospheric pressure chamber and carried out using off-oriented substrates prepared by a modified Lely method. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, Raman spectroscopy, photoluminescence(PL), scanning electron microscopy (SEM) and other techniques were utilized. The best quality of 4H-SiC homoepitaxial layers was observed in conditions of growth temperature 1500$^{\circ}C$ and C/Si flow ratio 2.0 of C3H3 0.2sccm & SiH4 0.3sccm. The growth rate of epilayers was about 1.0$\mu\textrm{m}$/h in the above growth condition.

• 한국세라믹학회지
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• 제38권12호
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• pp.1150-1154
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• 2001

플라즈마 화학기상증착(PECVD)법을 이용하여 실리카 광도파막의 코어로 이용되는 규소질산화막(SiON)을 Si 웨이퍼 위에 SiH$_4$,$N_2$O, $N_2$가스를 혼합하여 저온(32$0^{\circ}C$)에서 증착하였다. Prism coupler 측정을 통해 SiON 굴절률 1.4663~1.5496을 얻었으며, SiH$_4$/($N_2$O+$N_2$) 유량비와 rf power가 각각 0.33과 150W에서 8.67$mu extrm{m}$/h의 증착률을 나타내었다. 또한 SiH$_4$/($N_2$O+$N_2$) 유량비가 감소함에 따라 SiON막의 roughness는 41~6$\AA$까지 감소하였다.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.576-581
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• 2005

강유전체$(SrTiO_3)$ 박막을 게이트 절연층으로 하여 수소화 된 비정질 실리콘 박막 트랜지스터를 유리 기판 위에 제조하였다. 강유전체는 기존의 $SiO_2,\;SiN$ 등과 같은 게이트 절연체에 비하여 유전특성이 매우 뛰어나 TFT의 ON 전류를 증가시키고 문턱전압을 낮추며 항복특성을 개선하여 준다. PECVD에 의하여 증착된 a-Si:H는 FTIR 측정 결과 $2,000cm^{-1}$과 $876cm^{-1}$에서 흡수 밴드가 나타났으며, $2,000cm^{-1}$과 $635cm^{-1}$은 $SiH_1$의 stretching과 rocking 모드에 기인한 것이며 $876cm^{-1}$의 weak 밴드는 $SiH_2$ vibration 모드에 의한 것이다. a-SiN:H는 optical bandgap이 2.61 eV이고 굴절률은 $1.8\~2.0$, 저항률은 $10^{11}\~10^{15}\Omega-cm$ 정도로 실험 조건에 따라 약간 다르게 나타난다. 강유전체$(SrTiO_3)$ 박막의 유전상수는 $60\~100$ 정도이고 항복전계는 IMV/cm 이상으로 우수한 절연특성을 갖고 있다. 강유전체를 이용한 TFT의 채널 길이는 $8~20{\mu}m$, 채널 넓이는 $80~200{\mu}m$로서 드레인 전류가 게이트 전압 20V에서 $3.4{\mu}A$이고 $I_{on}/I_{off}$ 비는 $10^5\~10^8,\;V_{th}$는 $4\~5\;volts$이다.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.63.2-63.2
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• 2010

삼중접합 태양전지에 상부전지로 이용되는 a-SiO:H 태양전지는 PECVD(Plasma Enhanced Chemical Vapour Deposition)을 이용하여 증착하였다. i a-SiO:H는 $CO_2/SiH_4$ 비율을 변화하여 밴드갭을 조절하였다. $CO_2/SiH_4$가 0에서 0.43으로 증가 할수록 밴드갭이 1.74 eV에서 1.94 eV로 증가하는 경향을 보였다. 이는 FTIR에서 나타난 결과인 Si-O-Si 결합의 증가 때문인 것으로 판단한다. 그에 반해서 광 전도도는 감소하는 경향을 보였다.그러나 암전도도와 광전도도의 비율인 광민감도는 $10^5$에서 $10^4$의 값으로 비정질 태양전지에 적용가능한 값을 보였다. 이러한 박막 특성을 가진 i a-SiO:H를 이용하여 비정질 실리콘 태양전지를 제작한 결과 $CO_2/SiH_4$의 비율이 증가함에 따라 태양전지의 $V_{oc}$가 0.8 V에서 0.5 V로 현저하게 감소하였고, $J_{sc}$와 FF 역시 11 $mA/cm^2$에서 4 $mA/cm^2$, 69%에서 50%로 감소하였다. 단위박막 결함을 측정하는 CPM(Constant Photocurrent Method)을 이용하여 i a-SiO:H 내부에 $10^{16}cm^{-3}$ 정도의 내부 결함을 관찰하였고 이는 태양전지의 특성 감소와 관련이 있는 것으로 판단한다.

• 한국전기전자재료학회논문지
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• 제35권6호
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 추계학술대회 초록집
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• pp.64.1-64.1
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• 2011

다중접합 태양전지는 흡수대역이 다른 juntion으로 구성되어, 각각의 태양전지 간의 전류정합(current matching)이 효율 향상에 중요하다. 본 실험에서는 Top cell에 i-a-Si:H(Thinckness:100nm), Middle cell에는 i-a-SiGe:H(Thickness:800nm)을 적용하였고, bottom cell에는 i-${\mu}c$-Si:H(Thickness:1800nm), 수광부의 p-layer에 에 SiOx을 이용하여 triple juntion amorphous silicon solar cell(삼중접합태양전지)을 구현하였다. 이를 최적화 시키기 위해 ASA simulation을 이용하여 각 Cell의 intrinsic layer의 밴드갭을 가변하였다. 가변 결과 i-a-Si:H : 1.85 eV, i-a-SiGe:H: 1.6 eV, i-${\mu}c$-Si:H: 1.4 eV에서 태양전지 효율 14.5 %을 기록 하였다. 본 연구를 통해 Triple juntion cell에서의 intrinsic layer의 밴드갭 최적화를 구현해 볼 수 있었다.

• 한국재료학회지
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• 제19권2호
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• pp.90-94
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• 2009

The development of low-k materials is essential for modern semiconductor processes to reduce the cross-talk, signal delay and capacitance between multiple layers. The effect of the $CH_4$ concentration on the formation of SiOC(-H) films and their dielectric characteristics were investigated. SiOC(-H) thin films were deposited on Si(100)/$SiO_2$/Ti/Pt substrates by plasma-enhanced chemical vapor deposition (PECVD) with $SiH_4$, $CO_2$ and $CH_4$ gas mixtures. After the deposition, the SiOC(-H) thin films were annealed in an Ar atmosphere using rapid thermal annealing (RTA) for 30min. The electrical properties of the SiOC(-H) films were then measured using an impedance analyzer. The dielectric constant decreased as the $CH_4$ concentration of low-k SiOC(-H) thin film increased. The decrease in the dielectric constant was explained in terms of the decrease of the ionic polarization due to the increase of the relative carbon content. The spectrum via Fourier transform infrared (FT-IR) spectroscopy showed a variety of bonding configurations, including Si-O-Si, H-Si-O, Si-$(CH_3)_2$, Si-$CH_3$ and $CH_x$ in the absorbance mode over the range from 650 to $4000\;cm^{-1}$. The results showed that dielectric properties with different $CH_4$ concentrations are closely related to the (Si-$CH_3$)/[(Si-$CH_3$)+(Si-O)] ratio.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 추계 학술발표 강연 및 논문 개요집
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• pp.39-39
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• 1994

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.