• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.254-254
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• 2011

현재 AMLCD(Active Matrix Liquid Crystal Display)는 노트북, 컴퓨터, TV등 여러 영상매체에 있어 가장 많이 활용되고 있는 디스플레이로 손꼽힌다. AMLCD에 구동소자로 사용되는 a-Si:H TFT는 낮은 제조비용과 축적된 기술을 바탕으로 가장 많이 쓰이고 있다. 특히 a-Si이 가지는 소형화나 대형화의 편의성은 모바일 기기, projection TV, 광고용 패널 등 적용분야가 점점 넓어지고 있는 추세이다. 하지만 a-Si라는 물질 자체가 가지는 낮은 이동도는 더 많은 application을 위해 해결되어야 할 과제이다. 낮은 이동도는 a-Si 실리콘 원자간 결합의 불규칙성 및 무질서와 dangling bond에 의한 localize state(deep trap, band tail)의 존재 때문에 발생하며 결과적으로 TFT 소자의 특성의 저하를 가져온다. 앞선 연구에서는 carrier이동도의 개선을 위해서 첫 번째로 insulator층과 active층 사이의 계면 상태를 향상시키기 위해 insulator로 쓰이는 a-SiN층 표면에 0~18 sccm의 유량으로 phosphorus를 주입하였다. AFM분석을 해본 결과 phosphorus를 주입함으로써 계면의 roughness가 줄어드는 것을 확인 할 수 있었다. 이러한 계면의 roughness 감소는 표면 산란(surface scattering)및 전자 포획(trap)의 영향을 줄임으로써 이동도의 향상을 가져왔다. 두 번째로 active층으로 쓰이는 a-Si:H 층의 표면에 phosphorus를 0?9sccm의 유량으로 doping하였다. 이로 인해 channel이 형성되는 active 영역에 직접적으로 불순물을 doping됨으로써 전도도를 증가되어 이동도를 향상시켰다. 하지만 지나친 doping은 불순물 산란(impurity scattering)의 증가로 인해 이동도를 저하시키는 결과를 보여 주었다. 본 연구에서는 TFT의 이동도 향상을 위해 두 가지의 technology를 함께 적용시켜 a-SiN/a-Si:H 계면 각각에 phosphorus를 주입 및 doping을 하였다. 모든 박막은 PECVD로 제작하였으며 각 박막의 두께는 a-SiN/a-SiN(phosphorus)/a-Si:H(doped)/a-Si:H/n+ a-Si($2350{\AA}/150{\AA}/150{\AA}/1850{\AA}/150{\AA}$)으로 고정하고 유량을 변화시키면서 특성을 관찰하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.264-268
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• 2005

A 2.2-inch QCIF+(176${\times}$RGB${\times}$220) TFT-LCD with integrated row driver was developed using a standard amorphous silicon TFT technology. At low temperature, the integrated row driver operation is dramatically effected by the electron drift mobility reduction(■50 %) and the threshold voltage shift (■1V) of the a-Si TFT. We studied the dependency of circuit design and found that higher on-current circuit is important to guarantee good operation in wide temperature range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.559-562
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• 2004

A 2.2-inch QCIF+ $(176{\times}RGB{\times}220)$ TFT-LCD with integrated row driver was developed using a standard amorphous silicon TFT technology. At low temperature $({\sim}-20^{\circ}C)$, the integrated row driver operation is dramatically effected by the electron drift mobility variation $({\sim}50%)$ and the threshold voltage shift $({\sim}1V)$ of the a-Si TFT. We studied the temperature dependency of the circuit design and found that higher on-current circuit is important to guarantee good operation in wide temperature range.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.247-249
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• 2008

Low Temperature a-Si:H TFT on stainless steel substrate has been developed for the flexible electrophoretic display. Stability of low temperature a-Si:H TFT is more important point than its initial device characteristics. Thus, we have studied device characteristics of low temperature a-Si:H TFT in terms of stability for driving electrophoretic display.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.470-473
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• 2009

We have developed a novel driving method, Six times Rate Driving(SRD) for the purpose of making cost competitive TFT-LCD. By applying SRD method to an a-Si TFT-LCD, the driving rate was increased six times as it was named but the number of data lines and so its D-Ics were reduced to one sixth of the conventional one which resulted in the cost saving of that much. We also newly designed the gate driver in order to avoid any expansion of the bezel width caused by applying SRD. Our newly developed driving technology, SRD was successfully applied to 7.0-inch WSVGA (1024 ${\times}$ 600) TFT-LCD which can be driven with only one data D-IC and here introduced.