• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.793-798
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• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.62-70
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• 1984

N+NPP+ HLEBSF (high low emitter back surface field) solar cells which have N+N high low junction in the emitter as well as N+PP+ BSF cells were designed and fabricated by using <111> oriented P type Si wafers with the resistivity of 10$\Omega$/$\textrm{cm}^2$ and the thickness of 13-15 mil. Physical parameters (impurity concentration, thickness) at each region of N+PP+ and N+NPP+ cell were made equally through same masks and simultaneous process except N region of HLEBSF cell to investigate the high low emitter junction effect for efficiency improvement. Under the light intensity of 100 mW/$\textrm{cm}^2$, total area (active area) conversion efficiency were typically 10.94% (12.16%) for N+PP+ BSF cells and 12.07% (13.41%) for N+N PP+ cells. Efficiency improvement of N+NPP+ cell which has high low emitter Junction structure is resulted from the suppression of emitter recombination current and the increasement of open circuit voltage (Voc) and short circuit current (Ish) by removing heavy doping effects occurring in N+ emitter region.

• Proceedings of the Korean Nuclear Society Conference
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• 2005.05a
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• pp.75-76
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• 2005

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.387-400
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• 2017

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.102-106
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• 2005

A low dark current CMOS image sensor (CIS) pixel without any process modification is developed. Dark current is mainly generated at the interface region of shallow trench isolation (STI) structure. Proposed pixel reduces the dark current effectively by separating the STI region from the photodiode junction using simple layout modification. Test sensor array that has both proposed and conventional pixels is fabricated using 0.18 m CMOS process and the characteristics of the sensor are measured. The result shows that the dark current of the proposed pixel is 0.93fA/pixel that is two times lower than the conventional design.

• ETRI Journal
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• v.18 no.4
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• pp.301-313
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• 1997

We have found that in the ballistic electron transport in a ring structure, the junction-backscattering contribution is critical for all the major features of the Aharonov-Bohm-type interference patterns. In particular, by considering the backscattering effect, we present new and clear interpretation about the physical origin of the secondary minima in the electrostatic Aharonov-Bohm effect and that of the h/2e oscillations when both the electric and magnetic potentials are present. We have devised a convenient scheme of expanding the conductance by the junction backscattering amplitude, which enables us to determine most important electron paths among infinitely many paths and to gain insight about their contributions to the interference patterns. Based on the scheme, we have identified various interesting interference phenomena in the ballistic ring structure and found that the backscattering effect plays a critical role in all of them.

• Journal of electromagnetic engineering and science
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• v.13 no.4
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• pp.214-223
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• 2013

This paper proposes a theoretical analysis of hidden device detection and a design of multiband circular polarization patch array antenna for non-linear junction detector system application. A good axial ratio of circular polarization patch antenna is realized by a new approach that employs inclined slots, two rectangular grooves and a truncated ground for the conventional antenna. A good axial ratio of the 1.5 dB lower is measured by having an asymmetric gap distance between the ground planes of the coplanar waveguide feeding structure. The common ground plane of the linear array has an optimum trapezoidal slot array to reduce the mutual coupling without increasing the distance between the radiators. The higher gain of about 1 dBi is realized by using the novel common ground structure. The measured return loss, gain, and axial ratio of the proposed single radiator, as well as the proposed array antennas, showed a good agreement with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.105-110
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• 2005

In this paper, a new technique to reduce the phase noise in microwave oscillators is proposed using the resonant characteristics of the Photonic Bandgap(PBG). We applied PBG structure to ground of the microstrip line resonator with the low Q(Quality factor). Therefore, we improved about 10 dBc in contrast to phase noise characteristic of the conventional microstrip line oscillator at 2.4 GHz ＠ 100 MHz offset. Output power is 7.09 dBm.