• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.52-59
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• 2010

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.14-21
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• 2009

In this paper, a Ka-band 10 W power amplifier module with seven power MMIC bare dies is designed and fabricated using MIC technology which combines multiple MMIC chips on a thin film substrate. Modified Wilkinson power dividers/combiners and CBFGCPW-Microstrip transitions for suppressing resonance and reducing connection loss are utilized for high-gain and high-power millimeter wave modules. A new TTL pulse timing control scheme is proposed to improve output power degradation due to large bypass capacitors in the gate bias circuit. Pulse-mode operation time is extended more than 200 nsec and output power increase of 0.62 W is achieved by applying the proposed scheme to the Ka-band 10 W power amplifier module operating in the pulsed condition of 10 kHz and $5\;{\mu}sec$. The implemented power amplifier module shows a power gain of 59.5 dB and an output power of 11.89 W.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.169-177
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• 2012

A non-decimation second-order spatial moving average (SMA) discrete-time (DT) filter is proposed with reconfigurable null frequencies. The filter coefficients are changeable, and it can be controlled by switching sampling capacitors. So, interferers can be rejected effectively by flexible nulls. Since it operates without decimation, it does not change the sample rate and aliasing problem can be avoided. The filter is designed with variable weight of coefficients as $1:{\alpha}:1$ where ${\alpha}$ varies from 1 to 2. This corresponds to the change of null frequencies within the range of fs/3~fs/2 and fs/2~2fs/3. The proposed filter is implemented in the TSMC 0.18-${\mu}m$ CMOS process. Simulation shows that null frequencies are changeable in the range of 0.38~0.49fs and 0.51~0.62fs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.837-843
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• 2008

This paper proposes a power divider based on meta-material structure with dual-band operation. The meta-material structures of left-hand characteristic are constituted of series capacitors and shunt inductors, but they have parasitic series inductance and shunt capacitance effects. There is represented the composite right/ left-handed transmission line (CRLH-TL) model. When the power divider is implemented by using the CRLH-TL, the power divider can operate dual band. To verify the power divider with dual band, we are implemented to operate dual-band that is 0.88 GHz and 1.67 GHz. The characteristics of divider have the return loss less than each 21.0 dB and 15.8 dB and the insertion loss better than 3.83 dB and 3.64 dB at each frequency. Also, the output phase difference is $3{\sim}6^{\circ}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.157-160
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• 2004

Ferroelectric $(Ba_xSr_{1-x})TiO_3$ (BST) thin films have been deposited on (001) MgO single crystals by a pulsed laser deposition (PLD) method. The structure of deposited BST thin films were investigated by an x-ray diffractometer. Calculated c-axis lattice parameters of the BST films exhibit a strong lattice distortion, which was not observed in ceramic BST at room temperature. This lattice distortion of BST has been attributed to strains caused by lattice constant difference between film and substrate, oxygen vacancies in BST film, and thermal expansion difference between film and substrate. Ferroelectric properties at 10 GHz have been measured using a HP 8510C vector network analyzer. Dielectric properties, capacitance tunability and quality factor, of the interdigitaed capacitors fabricated on BST films were calculated from the measured s-parameters. Two distinct behaviors in structural, opitical, and microwave properties of BST films were observed; below and above 200 mTorr of oxygen pressure in the deposition chmber.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.48.2-48.2
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• 2010

The effect of additives as rare-earth in dielectric materials has been studied to meet the development trend in electronics on the miniaturization with increasing the capacitance of MLCCs (multi-layered ceramic capacitors). It was reported that the addition of rare-earth oxides in dielectrics would contribute to enhance dielectric properties and high temperature stability. Especially, dysprosium and thulium are well known to the representative elements functioned as selective substitution in barium titanate with perovskite structure. The effects of these additives on microstructure and electric properties were studied. The 0.8 mol% Dy doped $BaTiO_3$ and the 1.0 mol% Tm doped $BaTiO_3$ had the highest electric properties as optimized composition, respectively. According to the increase of rare-earth contents, the growth of abnormal grains was suppressed and pyrochlore phase was formed in more than solubility limits. Furthermore, the effect of two rare-earth elements co-doped $BaTiO_3$ on the dielectric properties and insulation resistance was investigated with different concentration. The dielectric specimens with $BaTiO_3-Dy_2O_3-Tm2O_3$ system were prepared by design of experiment for improving the electric properties and sintered at $1320^{\circ}C$ for 2h in a reducing atmosphere. The dielectric properties were evaluated from -55 to $125^{\circ}C$ (at $1KHz{\pm}10%$ and $1.0{\pm}0.2V$) and the insulation resistance was examined at 16V for 2 min. The morphology and crystallinity of the specimens were determined by microstructural and phase analysis.

• Korean Journal of Materials Research
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• v.17 no.11
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• pp.574-579
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• 2007

Amorphous $BaTi_4O_9$ ($BT_4$) film was deposited on Pt/Si substrate by RF magnetron sputter and their dielectric properties and electrical properties are investigated. A cross sectional SEM image and AFM image of the surface of the amorphous $BT_4$ film deposited at room temperature showed the film was grown well on the substrate. The amorphous $BT_4$ film had a large dielectric constant of 32, which is similar to that of the crystalline $BT_4$ film. The leakage current density of the $BT_4$ film was low and a Poole-Frenkel emission was suggested as the leakage current mechanism. A positive quadratic voltage coefficient of capacitance (VCC) was obtained for the $BT_4$ film with a thickness of <70 nm and it could be due to the free carrier relaxation. However, a negative quadratic VCC was obtained for the films with a thickness ${\geq}96nm$, possibly due to the dipolar relaxation. The 55 nm-thick $BT_4$ film had a high capacitance density of $5.1fF/{\mu}m^2$ with a low leakage current density of $11.6nA/cm^2$ at 2 V. Its quadratic and linear VCCs were $244ppm/V^2$ and -52 ppm/V, respectively, with a low temperature coefficient of capacitance of $961ppm/^{\circ}C$ at 100 kHz. These results confirmed the potential suitability of the amorphous $BT_4$ film for use as a high performance metal-insulator-metal (MIM) capacitor.

• Korean Journal of Materials Research
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• v.30 no.10
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• pp.495-501
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• 2020

The various sintered samples comprising of 72 wt% (Al₂O₃) : 28 wt% (SiO₂) based ceramics were fabricated using a colloidal processing route. The phase analysis of the ceramics was performed using an X-ray diffractometer (XRD) at room temperature confirming the presence of Al₂O₅Si and Al_5.33Si_0.67O_9.33. The surface morphology of the fracture surface of the different sintered samples having different sizes of grain distribution. The resistive and capacitive properties of the three different sintered samples at frequency sweep (1 kHz to 1 MHz). The contribution of grain and the non-Debye relaxation process is seen for various sintered samples in the Nyquist plot. The ferroelectric loop of the various sintered sample shows a slim shape giving rise to low remnant polarization. The excitation performance of the sample at a constant electric signal has been examined utilizing a designed electrical circuit. The above result suggests that the prepared lead-free ceramic can act as a base for designing of dielectric capacitors or resonators.