• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.840-841
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• 2008

Power capacitors are widely used to compensate the low power factor of the linear load and/or nonlinear load. Especially, nonlinear loads generates the harmonic current and it gives an undesirable effect on the power capacitors. In this paper, harmonic current from nonlinear load to the power capacitors is calculated by the computer simulation and it is compared with the experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.561-563
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• 2012

In this work, tunable capacitors using a finger-type electrode are designed and characterized for frequency-agile RF circuit applications. Their top electrodes with different area and line width are designed in types of the finger for a long conducting perimeter which results in enhanced fringing-electric fields in order to improve their tunability. The tunable varactors were fabricated on a quartz substrate employing a multi-layer dielectric of a para/ferro/para-electric thin film. Compared to the conventional capacitor, finger-type capacitors are characterized in terms of effective capacitance and tunablility. Their effective capacitance and tunability with the long perimeter increase 24~40% and 7~12%, respectively, due to enhanced fringing electric fields from 1 to 2.5 GHz, compared to the conventional ones.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.630-634
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• 2003

This paper proposes a Carrier-Rotation PWM technique that is new solution for the voltage unbalancing problem of flying capacitors in the Flying Capacitor Multi-level Inverter (FCMI).The proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of flying capacitors during one switching period of all the switches. it also has the same switch utilization and the reduced harmonics of output voltage. Hence, it is more suitable for the FCMI compared with the conventional solutions. Experimental results on the laboratory prototype flying capacitor 3-level inverter confirm the validity of the proposed PWM technique.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.267-270
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• 2003

In this paper, a new energy recovery circuit for AC PDP(Plasma Display Panel) is proposed to decrease a sustain voltage and voltage stress on switching elements. In the proposed circuit, two auxiliary capacitors are connected directly to the power source through switching elements and inductors when ground potential is supplied to the panel. Therefore, the voltage across auxiliary capacitors can be increased by turns over the half of the source voltage. Because the intrinsic capacitance of PDP is charged sufficiently from the auxiliary capacitors, the level of sustain voltage and the voltage stress on the switching devices are decreased. To verify the validity of the proposed energy recovery circuit, computer simulations using PSpice program are carried out.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1752-1762
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• 2016

To achieve higher reliability in the modular multilevel converters (MMC) for HVDC transmission systems, the internal condition of the DC capacitors of the submodules (SM) needs to be monitored regularly. For an online estimation of the SM capacitance, a controlled AC current with double the fundamental frequency is injected into the circulating current loop of the MMC, which results in current and voltage ripples in the SM capacitors. The capacitor currents are calculated from the arm currents and their switching states. By processing these AC voltage and current components with digital filters, their capacitances are estimated by a recursive least square (RLS) algorithm. The validity of the proposed scheme has been verified by simulation results for a 300-MW, 300-kV HVDC system. In addition, its feasibility has been verified by experimental results obtained with a reduced-scale prototype. It has been shown that the estimation errors for both the simulation and experimental tests are 1.32% at maximum.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.7
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• pp.338-346
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• 2001

In this paper, dc link currents for the three-phase diode rectifiers and PWM inverters are analyzed and an algorithm of estimating the life of dc link electrolytic capacitors using the analyzed ripple current is presented. Since the capacitor life is dependent on the operating temperature, the power dissipation in capacitors should be calculated. For this, the ESR(equivalent series resistance) model of the capacitor is derived and ripple currents through the capacitor are analyzed. Relating the power dissipation and the heat transfer equation, the internal operating temperature is calculated. Then, the capacitor life can be predicted by using Arrhenius's equation. An example for applications is given for the practical system.

• Transactions on Electrical and Electronic Materials
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• v.8 no.2
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• pp.97-102
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• 2007

The charging/discharging characteristics of electric double layer capacitors (EDLCs) for an electric power storage device application were investigated. The specific area of the carbonaceous electrode surface by the BET method was in the range of $1800{\sim}2000\;m^2/g$. The charge distributions during charging and discharging were measured by means of a pulsed-electro-acoustic (PEA) method, and the voltage characteristics of EDLCs connected to solar cells were evaluated. The results showed that the distributions of positive and negative charges were spatially uneven, which was due to the mobility of the positive and negative charges in the carbonaceous electrode surface of the EDLCs. The charge accumulation region concentrated on central part of the carbonaceous electrode and the required times for charging and discharging were almost same.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.57-61
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• 1985

The e(lect of capacitance error on the A/D conversion accuracy in the A/D converter using binary-weighted capacitor array was scruntized. Besides the Monte-Carlo method considering the inter-capacitance ratios as random variables, " correlation approach" con-sidering the correlation coefficient between capacitances is proposed in this paper. Bt was observed by the measurement of capacitances of monolithic MO5 capacitors that the correla-tion coefficient between capacitors decreases as the capacitor size incrrases. It was also verified that the parallel connection of unit capacitors and the common centroid layout scheme signi(icantly increase the inter-capacitance correlation coefficients.