• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.237-241
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• 2008

An all-optical encryption system built on the basis of electrical logic circuit design principles is proposed, using semiconductor optical amplifier (SOA) exclusive or (XOR) logic gates. Numerical techniques (steady-state and dynamic) were employed in a sequential manner to optimize the system parameters, speeding up the overall design process. The results from both numerical and experimental testbeds show that the encoding/decoding of the optical signal can be achieved at a 10 Gbps data rate with a conventional SOA cascade without serious degradation in the data quality.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.262-270
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• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.892-894
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• 2002

본 논문은 유한 체 GF(/2 sup m/)상에서 A$B^2$연산을 위해 AOP(All One Polynomial)에 기반한 새로운 MSB(Most Significant bit) 유선 알고리즘을 제시하고, 제시한 알고리즘에 기반하여 병렬 입출력 세미시스톨릭 구조를 제안한다. 제안된 구조는 표준기저(standard basis)에 기반하고 모듈라(modoular) 연산을 위해 다항식의 계수가 모두 1인 m차의 기약다항식 AOP를 사용한다. 제안된 구조에서 AND와 XOR게이트의 딜레이(deray)를 각각 /D sub AND$_2$/와/D sub XOR$_2$/라 하면 각 셀 당 임계경로는 /D sub AND$_2$+D sub XOR/이고 지연시간은 m+1이다. 제안된 구조는 기존의 구조보다 임계경로와 지연시간 면에서 보다 효율적이다. 또한 구조 자체가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI 구현에 효율적이다. 더욱이 제안된 구조는 유한 체상에서 지수 연산을 필요로 하는 Diffie-Hellman 키 교환 방식, 디지털 서명 알고리즘 및 EIGamal 암호화 방식과 같은 알고리즘을 위한 기본 구조로 사용할 수 있다. 이러한 알고리즘을 응용해서 타원 곡선(elliptic curve)에 기초한 암호화 시스템(Cryptosystem)의 구현에 사용될 수 있다.

• Korean Journal of Optics and Photonics
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• v.17 no.6
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• pp.564-568
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• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.25-27
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• 1984

Using LED sources, the system that performs optical logic function of the input data arrays will be presented. Sixteen possible functions of two binary data arrays, such as AND, OR, NOR and XOR are simply obtained in parallel by controlling LED switching mode. Experimental result and some examples of application will be given.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.