• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.336-339
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• 2012

본 논문에서는 비선형 MLCA(Maximum Length Cellular Automata)와 1D CAT(One-Dimensional Cellular Automata Transform)를 이용하여 의료 영상 암호화 방법을 제안한다. 암호화 방법은 먼저, Wolfram Rule 행렬에 의해 전이행렬 T를 생성한다. 그 후, 암호화하려는 원 영상에 생성된 전이 행렬 T를 곱하여 원 영상의 픽셀 값을 변환한다. 또한 변환된 원 영상을 여원 벡터 F와 XOR 연산하여 비선형 MLCA가 적용된 영상으로 변환한다. 다음, 게이트웨이 값을 설정하여 1D CAT 기저함수를 생성한다. 그리고, 비선형 MLCA가 적용된 영상에 생성된 1D CAT 기저함수를 곱하여 암호화를 한다. 마지막으로 키 공간 분석을 통하여 제안한 방법이 높은 암호화 수준의 성질을 가졌음을 검증한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.339-340
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• 2018

본 논문에서는 경량 블록암호 알고리듬 TWINE의 하드웨어 설계에 대해 기술한다. TWINE은 80-비트 또는 128-비트의 마스터키를 사용하여 64-비트의 평문(암호문)을 암호(복호)하여 64-비트의 암호문(평문)을 만드는 대칭키 블록암호이며, s-box와 XOR만 사용하므로 경량 하드웨어 구현에 적합하다는 특징을 갖는다. 암호화 연산과 복호화 연산의 하드웨어 공유를 통해 게이트 수가 최소화 되도록 구현하였으며, 설계된 TWINE 크립토 코어는 RTL 시뮬레이션을 통해 기능을 검증하였다.

• ETRI Journal
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• v.13 no.2
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• pp.9-14
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• 1991

직병렬 승산기는 피승수와 승수중 어느 하나가 병렬로 입력되고 또다른 수는 직렬로 입력되는 구조를 가지며, 디지틀 신호처리, 온라인 응용, 특수 목적용 계산 시스팀 등에서 많이 이용되고 있다. 본 논문에서는 2 의 보수를 위한 직병렬 승산기의 논리구조를 제안한다. 제안한 2의 보수 직병렬 승산기는 효과적인 2의 보수 직병렬 승산 알고리즘에 의해서 모든 데이터 신호가 국부적 연결만으로 구성되며, 간단하고 모듈화된 하드웨어의 구성으로 쉽게 설계할 수 있다. 이 승산기는 무부호 승산과 마찬가지로 2n+1 사이클만을 필요로 하고, 각 사이클 시간은 무부호 직병렬 승산에 비해서 2의 보수 승산을 위한 XOR 게이트의 지연시간이 추가된 것뿐이다. 또한, 제안한 2의 보수 직병렬 승산기는 VLSI 구현에 매우 적합한 구조를 지닌다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.55-60
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• 2007

This paper presents a compact double resolution scheme for the optical angle sensor based on 1-dimensional CMOS photodiode pixel array. All the pixels are divided into the even pixel and the odd pixel groups. The winner take all circuit is provided for each group. The proposed interpolation scheme increases the resolution by 2 from the winner addresses and winner values. The interpolation scheme can be implemented without any additional pixels or winner take all circuits and require only a comparator and a XOR gate. The proposed pixel array chip that has 336 photodiode pixels with $5.6{\mu}m$ pitch was fabricated with $0.35{\mu}m$ CMOS process and was assembled with a $50{\mu}m$ slit to form an angle sensor. The measured resolution is $0.1{\circ}$ with the proposed interpolation. The chip consumes 35mW and provides 8k samples per second.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.33-41
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• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6C
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• pp.361-367
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• 2011

In this paper, we propose encryption method to using complemented MLCA(Maximum Length Cellular Automata) based on NBCA(Null Boundary CA) and 2D CAT (Two-Dimensional Cellular Automata Transform) for efficient image encryption. The encryption method is processed in the following order. First, a transition matrix T is created using the Wolfram Rule matrix. Then, the transition matrix T is multiplied to the original image that is intended to be encrypted, which transfers the pixel values of the original image. Furthermore, the converted original image goes through a XOR operation with complemented vector F to convert into a complemented MLCA applied image. Then, the gateway value is set and 2D CAT basis function is created. Also, the 2D CAT is encrypted by multiplying the created basis function to the complemented MLCA applied image. Lastly, the stability analysis verifies that proposed method holds a high encryption quality status.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.34-41
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• 2009

In this paper we propose a new image encryption method which utilizes Complemented MLCA(Complemented Maximum Length Cellular Automata) based on IBCA(Intermediate Boundary CA) and 2D CAT(Cellular Automata Transform). The encryption method is processed in the following order. First, Complemented MLCA is used to create a PN (pseudo noise) sequence, which matches the size of the original image. And, the original image goes through a XOR operation with the created sequence to convert the image into Complemented MLCA image. Then, the gateway value is set to produce a 2D CAT basis function. The produced basis function is multiplied by the encrypted MLCA image that has been converted to process the encipherment. Lastly, the stability analysis and PSNR(Peak Signal to Noise Ratio) verifies that the proposed method holds a high encryption quality status.