• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.2
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• pp.81-87
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• 2000

This paper presents a new approach to the synthesis of two-dimensional arrays such as Atmel 6000 series FPGAs using internal don't cares. Basically complex terms which fits to the linear array of cells without further routing wires are generated and they are collected by OR/XOR operations. In previous methods, complex terms are collected only by XOR operations, which may not be effective for nearly unate functions. In this paper, we allow complex terms to be collected by OR operations in addition to XOR operations. First, complex terms that lies in the ON-set of the function are generated and collected by OR operations. The sub-function realized by the first stage becomes an internal don't cares and they are exploited in the second stage which generates complex terms collectable by XOR operation. Experimental results shows the efficacy of the proposed method compared to the previous methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Convergence Security Journal
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• v.7 no.1
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• pp.55-62
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• 2007

In ubiquitous environment the authentication protocol design for RFID security is studied to protect user privacy in RFID system. The XOR-based approach of RFID security is implemented inexpensively and simply. However because of using same security informations, ones of tag is disclosed easily. In this paper, we enhance the previous XOR-based authentication protocol using a circular shift operation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.3
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• pp.109-116
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• 2007

In this paper, we analyse the security of the variant of Self-Shrinking generator proposed by Chang et al. against a guess-and-determine attack. This variant, which we call SSG-XOR is claimed to have better cryptographic properties than the Self-Shrinking generator in a practical setting. But we show that SSG-XOR is weaker than the Self-Shrinking generator from the viewpoint of guess-and-determine attack.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Korean Journal of Optics and Photonics
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• v.17 no.6
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• pp.564-568
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• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.623-629
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• 2003

In this paper, we have proposed a full phase encryption scheme based on phase-encoded XOR operation. The proposed scheme encrypts a gray-level image by slicing an original image and combining with XORed images which resulted from phase-encoded XOR operations between sliced images and phase-encoded binary random images. Then we produce an encrypted image by combining only XORed images and a key image by only phase-encoded binary random images. The encrypted image and key image are converted into encrypted data and key data by a phase-encoding method. The merits are that the proposed encryption scheme can basically fulfill a high-level encryption using a full phase encryption scheme which has nonlinear and invisible characteristics. The scheme also improves security by encrypting the phase information before full phase encryption. The decryption system based on the principle of interference between a reference wave and a direct pixel-to-pixel mapping image of encrypted data with key data can be simply implemented using a phase-visualization system. Simulation results indicate that our proposed encryption scheme is effective and simple for a gray-scale image and optical decryption system.