The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

A New Approach to the Synthesis of Two-Dimensional Cellular Arrays Using Internal Don't Cares

내부 Dont't care를 이용한 이차원 셀 배열의 새로운 합성 방법

  • Lee, Dong-Geon (Dept.of Computer Science, Graduate School of Chonnam National University) ;
  • Jeong, Mi-Gyeong (Dept.of Computer Science, Graduate School of Chonnam National University) ;
  • Lee, Gwi-Sang (Dept.of Computer Science, Graduate School of Chonnam National University)
  • Published : 2000.02.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a new approach to the synthesis of two-dimensional arrays such as Atmel 6000 series FPGAs using internal don't cares. Basically complex terms which fits to the linear array of cells without further routing wires are generated and they are collected by OR/XOR operations. In previous methods, complex terms are collected only by XOR operations, which may not be effective for nearly unate functions. In this paper, we allow complex terms to be collected by OR operations in addition to XOR operations. First, complex terms that lies in the ON-set of the function are generated and collected by OR operations. The sub-function realized by the first stage becomes an internal don't cares and they are exploited in the second stage which generates complex terms collectable by XOR operation. Experimental results shows the efficacy of the proposed method compared to the previous methods.

Keywords

References

  1. ATMEL Corporation CMOS Integrated Circuit Data Book. ATMEL, 1994
  2. U. Kebschull, E. Schubert, and W. Rosentiel. 'Multilevel logic synthesis based on functional decision diagram', In EDAC, page 43-47 ,1992 https://doi.org/10.1109/EDAC.1992.205890
  3. R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M. A. Perkowski. 'Efficient representation and manipulation of switching functions based on ordered kronecker functional decision diagrams', In Design Automation Conference, pages 415-419, 1994 https://doi.org/10.1145/196244.196444
  4. L. F. Wu and M. A. Perkwski, 'Minimization of permuted Reed-Muller trees for cellular logic programmable gate arrays', H. Gruenbacher and R, Hartenstein (eds.), LNCS, pages 78-87, 1993 https://doi.org/10.1007/3-540-57091-8_32
  5. A. Sarabi, N Song, M.Chrzanowska-jeske, and M. A. perkowski, 'A comprehensive approach to logic synthesis and physical design for two-dimensional logic arrays', In Design Automation Conference, pages 321-326, June 1994 https://doi.org/10.1145/196244.196398
  6. G. Lee, 'Logic synthesis for cellular architecture FP-GAs using BDDs', In ASP-DAC'97, pages 253-258, january 1997 https://doi.org/10.1109/ASPDAC.1997.600136
  7. K. K. Maitra, 'Cascaded swithcing networks of two-input flexible cells', IRE Trans. Electron. Com., pages 136-143, 1962
  8. T. Sasao, editor, 'AND-EXOR Expressions and Their Optimization', Kluwer Academic Publisher, 1993
  9. M. A. Perkowski, M. Chrzanowska - Jeske, A. Sarabi and I, 'Multi-level logic synthesis based on kronecker and boolean ternary decision diagrams for incompletely specified function', In VLSI Designs, 3(3), pges 301-313, 1995 https://doi.org/10.1155/1995/24594
  10. T. Kozlowski, E. L. Dagless, and J. M. Saul, 'An enhanced algorithm for the minimization of exclusive-or sum-of-products for incompletely specified functions', In ICCD, pages 244-249, 1995 https://doi.org/10.1109/ICCD.1995.528817