• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.121-130
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• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.109-118
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• 2007

Recently, flash memory is used to store data in mobile computing devices such as PDAs, SmartCards, mobile phones and MP3 players. These devices need index structures like the B-tree to efficiently support some operations like insertion, deletion and search. The BFTL(B-tree Flash Translation Layer) technique was first introduced which is for implementing the B-tree on flash memory. Flash memory has characteristics that a write operation is more costly than a read operation and an overwrite operation is impossible. Therefore, the BFTL method focuses on minimizing the number of write operations resulting from building the B-tree. However, we indicate in this paper that there are many rooms of improving the performance of the I/O cost in building the B-tree using this method and it is not practical since it increases highly the usage of the SRAM memory storage. In this paper, we propose a BOF(the B-tree On Flash memory) approach for implementing the B-tree on flash memory efficiently. The core of this approach is to store index units belonging to the same B-tree node to the same sector on flash memory in case of the replacement of the buffer used to build the B-tree. In this paper, we show that our BOF technique outperforms the BFTL or other techniques.

• Journal of KIISE:Databases
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• v.29 no.1
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• pp.34-43
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• 2002

Since traditional static metadata set like Dublin Core has static metadata attributes about bibliography information, integration of metadata for various metadata, problems about standard and extension of metadata must be considered for applying it to new environment. Specially, as event-driven metadata write method included the notion of e-commerce come out for interoperability in digital libraries, traditional metadata management which cannot distinguish between different kinds of update operations to new extension of metadata set occurs unsuitable waiting of update operation. So, improvement is needed about it. In this paper, we show whether alleviative transaction consistency can be applied to digital library or not. Also it would divide newer metadata into static metadata attribute connected in read operation within user read-only transaction and dynamic metadata attribute in update operation within dynamic(e-commerce) update transactions. We propose newer metadata management algorithm considered in classfication of metadata attributes and dynamic update transaction. Using two version for minimal maintenance cost and ARU(Appended Refresh Unit) for dynamic update transaction, to minimize conflict between read and write operations shows fast response time and high recency ratio. As a result of the performance evaluation, we show our algorithm is proved to be better than other algorithms in newer metadata environments.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.101-112
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• 2009

Existing techniques for defragmentation of the file system need intensive disk operation for some periods at specific time such as disk defragmentation program. In this paper, for solving this problem, we design and implement the automatic and continuous defragmentation free system by distributing the disk operation. We propose the Automatic Layout Scoring(ALS) mechanism for measuring defragmentation degree and suggest the Lazy Copy mechanism that copies the defragmented data at idle time for scattering the disk operation. We search the defragmented file by Automatic Layout Scoring mechanism and then find for empty spaces for that searched file. After lazy copy of searched fils to empty space for preventing that file from being lost, the algorithm solves the defragmentation problem by updating the I-node of that file. We implement these algorithms in Linux and evaluate them for small and defragmented file to get the layout scoring. We outperform the Linux EXT2 file system by $2.4%{\sim}10.4%$ in layout scoring evaluation. And the performance of read and write for various file size is better than the EXT2 by $1%{\sim}8.5%$ for write performance and by $1.2%{\sim}7.5%$ for read performance. We suggest this system for solving the problem of defragmentation automatically without disturbing the I/O task and manual management.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.1-10
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• 2016

Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.19-23
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• 2013

This paper deals with the analysis of 6T SRAM cell stability for Hi-speed processing Ternary Content Addressable Memory. The higher the operation frequency, the smaller CMOS technology required in the designed TCAM because the purpose of TCAM is high-speed data processing. Decrease of Supply voltage is one cause of unstable TCAM operation. Thus, We should design TCAM through analysis of SRAM cell stability. In this paper we propose methodology to characterize the Static Noise Margin of 6T SRAM. All simulations of the TCAM have been carried out in 180nm CMOS process technology.

• Transactions of the Society of Information Storage Systems
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• v.11 no.1
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• pp.16-21
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• 2015

An archive system is designed to store data for a long time without loss. However, many important factors such as temperature, dust, vibration, and humidity must be considered to design a successful archive system. Read/write devices, for example optical disk drives(ODDs), in an archive system generate heat while they are in operation. Fans are usually used to remove heat but the air flow accompanies dust into the system result in system failure. In this study, an archive system with six ODDs is chosen as an analysis model and flow together with temperature distributions are computed using a CFD simulation package. Flow analysis is focused on four cooling fans at the rear panel and temperature distribution is studied for various cases of fan operation. From the temperature point of view, fans give significant effects on $4^{th}$ to $6^{th}$ ODDs compared to the $1^{st}$ to $3^{rd}$ ODDs. Also, it is noticed which fan is the most important as far as cooling is concerned.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.177-182
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• 2003

In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.