• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.161-165
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• 1998

다중 프로세서 구조로 실시간 분산 처리를 하는 전전자 교환기 시스템은 그 특성상 2개 이상의 프로세서에 동일한 값을 유지하는 중복 데이터의 사용이 필수적이다. 시스템의 자원 정보, 번호 번역 정보, 과금 정보 등이 중복 데이터로 사용된다. 이러한 중복 데이터에 대한 변경은 불일치 상태를 회피하기 위해 그 처리에 많은 비용과 제한이 따른다. 과도한 시그널 전송 및 로그 저장, 재전송 알고리즘은 데이터베이스 시스템의 성능을 저하시키고 때때로 순간적인 마비 상태까지도 유발할 수 있다. 본 논문에서는 기존 일관성 방안의 문제점을 분석하고 단일-버스 다중-프로세서 시스템에서 각각의 캐쉬들간의 일관성 유지를 위한 write-through 캐쉬 일관성 프로토콜을 사용하여 저 비용이며 효율적인 중복 데이터 일관성 유지 방안을 제시한다.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• The Journal of Korean Institute of Next Generation Computing
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• v.14 no.5
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• pp.40-52
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• 2018

Solid state drive (SSD) cache technologies that are used as a second-tier cache between the main memory and hard disk drive (HDD) have been widely studied. The SSD cache requires a new prefetching scheme as well as cache replacement algorithms. This paper presents a prefetching scheme for a storage-class cache using SSD. This prefetching scheme is designed for the storage-class cache and based on a long-term scheduling in contrast to the short-term prefetching in the main memory. Traditional prefetching algorithms just consider only read, but the presented prefetching scheme considers both read and write. An experimental evaluation shows 2.3% to 17.8% of hit rate with a 64GB of SSD and the 4GiB of prefetching size using an I/O trace of 14 days. The proposed prefetching scheme showed significant improvement of cache hit rate and can be easily implemented in storage-class cache systems.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.66-74
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• 2008

Since modem embedded systems need to access, manipulate or store sensitive information, it requires being equipped with cryptographic file systems. However, cryptographic file systems result in poor performance so that they have not been widely adapted to embedded systems. Most cryptographic file systems degrade the performance unnecessarily because of system architecture. This paper proposes ISEA (Indexed and Separated Encryption Approach) that supports for encryption/decryption in system architecture and removes redundant performance loss. ISEA carries out encryption and decryption at different layers according to page cache layer. Encryption is carried out at lower layer than page cache layer while decryption at upper layer. ISEA stores the decrypted data in page cache so that it can be reused in followed I/O request without decryption. ISEA provides page-indexing which divides page cache into cipher blocks and manages it by a block. It decrypts pages partially so that it can eliminate unnecessary decryption. In synthesized experiment of read/write with various cache hit rates, it gives results suggesting that ISEA has improved the performance of encryption file system efficiently.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.143-150
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• 2013

Solid-state disks (SSDs) have been widely used by high-performance personal computers or servers due to its good characteristics and performance. The NAND flash-based SSDs, which take large portion of the whole NAND flash market, are the major type of SSDs. They usually integrate a cache buffer which is built from DRAM and uses the write-back policy for better performance. Unfortunately, the policy makes existing scheduling methods less effective at the I/F level of SSDs Therefore, in this paper, we propose a scheduling method for the I/F with consideration of the cache buffer. The proposed method considers the hit/miss status of cache buffer and gives higher priority to the read requests. As a result, the requests whose data is hit on the cache buffer can be handled in advance and the read requests which have larger effects on the whole system performance than write requests experience shorter latency. The experimental results show that the proposed scheduling method improves read latency by 26%.

• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.19-27
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• 2015

Due to the advantages of fast read/write operation and low power consumption, SSD(Solid State Drive) is now widely adopted as storage device of smart phone, laptop computer, server, etc. However, the shortcomings of SSD such as limited number of write operations and asymmetric read/write operation lead to the problem of shortened life span of SSD. Therefore, the block replacement policy of SSD used as cache for HDD is very important. The existing solutions for improving the lifespan of SSD including the LARC scheme typically employ the LRU algorithm to manage the SSD blocks, which may increase the miss rate in SSD due to the replacement of frequently used block instead of rarely used block. In this paper we propose a novel block replacement scheme which considers the block reuse interval to effectively handle various data read/write patterns. The proposed scheme replaces the block in SSD based on the recency decided by reuse interval and age along with hit ratio. Computer simulation using workload trace files reveals that the proposed scheme consistently improves the performance and lifespan of SSD by increasing the hit ratio and decreasing the number of write operations compared to the existing schemes including LARC.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.107-109
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• 2000

고속 LAN과 같은 통신 장비의 발달로 클라이언트/서버 시스템 환경이 일반화됨에 따라 데이터베이스 시스템도 클라이언트/서버 환경을 지원하는 데이터 서버로서의 역할이 요구되었다. 또한, 다양하고 복잡한 형태의 제어 시스템들이 필요한 각 응용 분야에서 클라이언트/서버 시스템이 이용되고 있다. 이러한 상황에서 클라이언트들은 통신 비용 절감과 서버의 부하를 줄이기 위해 클라이언트의 버퍼에 데이터의 사본을 캐쉬(cache) 함으로써 클라이언트 시스템의 확장성 및 독립성을 추구한다. 하지만, 캐쉬한 데이터의 사본에 의해 갱신 연산이 수행되기 때문에 캐쉬 데이터의 일관성 유지를 위한 효율적인 방법들이 필요하다. 본 논문에서 제안한 기법은 클라이언트/서버 간의 데이터 전송이 페이지 단위로 행해지는 페이지-서버 환경에서 적용되는 회피-기반(avoidance-based) 기법으로써, 클라이언트가 데이터를 갱신할 때 갱신 의도를 비동기적으로 선언하는 캐위 일관성 유지 기법을 제안하였다. 그리고 제안한 기법과 최근에 제안된 기법들을 비교 분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1599-1606
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• 1997

The software RAID file system is defined as the system which distributes data redundantly across an aray of disks attached to each workstations connected on a high-speed network. This provides high throughput as well as higher availability. In this paper, we present an efficient caching scheme for the software RAID filte system. The performance of this schmem is compared to two other schemes previously proposed for convnetional file systems and adapted for the software RAID file system. As in hardware RAID systems, small-writes to be the performance bottleneck in softwre RAID filte systems. To tackle this problem, we logically divide the cache into two levels. By keeping old data and parity val7ues in the second-level cache we were able to eliminate much of the extra disk reads and writes necessary for write-back of dirty blocks. Using track driven simulations we show that the proposed scheme improves performance for both the average response time and the average system busy time.