• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• The KIPS Transactions:PartA
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• v.10A no.2
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• pp.83-92
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• 2003

RAID 5 is a widely-used technique used to construct disk systems of high reliability and performance. This paper proposes APGOC (Adaptive Parity Group On Cache) organization on cache to solve "small write" problem of RAID 5 especially in OLTP (On-Line Transaction Processing System) environments. In our approach, when user process makes a request for a file to kernel, the information on the read/write characteristics is added to the file data structure of the file system. With this information, data and parity cache can be managed interchangeably through parity fetching. Therefore we can enhance the cache utilization and improve the disk request response time. Our method is analyzed and evaluated with a simulation method. Comparing with previous works, we observed about 6~l3% of performance enhancement.hancement.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3116-3123
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• 1999

Current disk systems are generally designed to reduce read traffic more effectively. Hence, write traffic of the I/O workload could potentially become a bottleneck of the disk system performance. In order to overcome this problem without much cost, this paper presents using outermost-zone track of multi-zoned recording disk as a secondary disk cache. The proposed disk cache improves the disk system performance by following exploitations: speed difference between block transfer and track transfer, difference in transfer rate between outermost-zone tracks and inner tracks, reduction in the seek time caused by decreasing the number of disk cache tracks, and idle period during burst accesses. In addition, it does not waste the disk space because it allocates the caching space by the cylinder unit. The simulation results show that the proposed system improves 2.54∼3.11 times better in terms of average response time for write operations than existing disk systems..

• Journal of KIISE
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• v.42 no.8
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• pp.972-978
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• 2015

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

• Journal of Industrial Technology
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• v.15
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• pp.103-111
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• 1995

In this paper we evaluate the performance of the cached RAID5 which uses the parity cache and the data cache to overcome the small write problem. From the result of the simulation study we show that the cached RAID5 provides performance improvement with reasonable cache size.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.289-297
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• 2020

Although flash disks are being used widely instead of hard disks, it is difficult to optimize for effective utilization of flash disks because overwrite in place is impossible and the power consumption and time required for read, write, and erase operations are all different. One of these optimization issues is a cache management strategy to minimize write operations. The cache operates at two levels: an operating system equipped with flash disks and a translation layer within the flash disk. Most studies deal with the operating system-level cache strategy. In this study, we implement and analyse the DPW-LRU algorithm which is one of the recently proposed operating system cache replacement algorithms to apply to FTL, and grope with some improvements. As a result of the experiment, the DPW-LRU algorithm maintained superiority even in the FTL environment, and showed better performance with a slight improvement.