• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.329-337
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• 1989

This paper describes a composition of time switch with a large capacity(NK byte) by multi-write method. The method arranged a basic unit in a plane and a group, which is composed by 1K byte time switch using a memory elements with a fixed access time and capacity. And the time switch of large capacity is composed by multi-write method, which is more than 8K byte capacity with many constraints by using today's semiconductor development techniques, then a basic unit is the 1K byte time switch using a CMOS SRAM with 62.5ns access time and 1K byte capacity.

• Journal of KIISE:Information Networking
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• v.31 no.3
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• pp.259-268
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• 2004

According to the increasing demand of application software that must be applied to the distributed computing environment, the various tools are proposed to write distributed softwares. But, if using these tools, programmers have to know the usage of each tool requisite for writing distributed softwares. If programmers can write distributed software without additional knowledge, they can get better concentration of the functions of software itself to develop, because it reduces burden for distributed programming. In this paper. we introduce new distributed programming tool, named TORB(Transparent Object Request Broker). With TORB, thanks to programming transparency that is supported by TORB, we can write the distributed software with java more easily. After postprocessing, this software can run in the distributed processing environment that is supported by TORB.

• Journal of KIISE:Software and Applications
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• v.32 no.11
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• pp.1036-1046
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• 2005

Cohesion refers to the degree of the relatedness of the members in a class and it is widely accepted that the higher the cohesion of a module is, the easier the module to understand and maintain. Recently, several cohesion measures have been proposed to measure the cohesiveness of classes in an object-oriented program. In this paper, we propose an approach to improving the existing cohesion measures by considering the impact of write dependencies between class members. We have developed a cohesion measurement tool for supporting our approach and describe a case study performed with a C++ class library.

• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.69-81
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• 2001

This paper describes a parallel programming environment to help programmer to write parallel programs. Parallel program must be write according to the character of the various hardware or program. So it is difficult for the programs to write the parallel programmer. In this paper, we propose and implement a parallel programming environment using graph type intermediate representation form, and graph user interface is provided for programmer to get parallel programs easily, This parallel environment supports special functions using graph type intermediate representation form. The special functions involve program editing. data dependence analysis, loop transformation. CFG, PDG, HTG. This parallel environment helps users make parallelism and optimization easy through showing the intermediate code with graph.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.19-26
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• 2010

The Windows registry is a hierarchical database where the configuration data of a system or application programs is stored. In this paper, we presented and implemented a registry virtualization algorithm and measured its performance. The registry virtualization algorithm presented in the paper is called Copy-One-level On Write-Open(COOWO) that is a modified version of general Copy On Whte(COW) method to make it suitable for registry virtualization. In this paper, we implemented the proposed algorithm as a dynamically loadable library in Windows and applied it to many Windows application programs. This paper is meaningful since we described a registry virtualization algorithm in detail in situation where we can not find papers that describe the registry virtualization in detail, and we could find the performance of the algorithm can be used in the real applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.50-59
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• 2000

This paper presents a new SRAM testing method for various faults by monitoring dynamic power supply currents. The peak value of Iddt pulses when the transition write operation is performed, is prominently different from that of a fault free case. Using the observation, a new memory test algorithm is developed which consists of only write operations. The new test algorithm using dynamic power supply current testing, has length of 7n, where n is the number of cells in SRAMs. Compared to the previous March B algorithm, the test length has been reduced by 7/17, and can detect additional hard-to-detect faults.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.117-123
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• 2013

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.58-64
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• 2013

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.121-126
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• 2004

In this paper, the effects of the ozone oxidation of the landing polycrystalline silicon on the cell contact resistance of the DRAM device were studied. For this study, the ozone oxidation of the landing polycrystalline silicon layer was performed under various conditions, which was followed by the normal DRAM processes. Then, the cell contact resistance and $t_{WR}$ (write recovery time) of the devices were measured and analyzed. The experimental results showed that the cell contact resistance was more significantly increased for higher temperature of oxidation, longer time of oxidation, and higher concentration of ozone in the oxidation furnace. In addition, the TEM cross-sectional micrographs clearly showed that the oxide layer at the interface between the landing polycrystalline silicon layer and the plug polycrystalline silicon layer was increased by the ozone oxidation. Furthermore, the rate of the device failure due to too large write recovery time was also found to be well correlated with the increase of the cell contact resistance.