• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.670-676
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• 2002

The object of ATM network is to the guarantee quality of service(QoS). Therefore, various of traffic management schemes have been proposed. Among these schemes, call admission control(CAC) is very important to provide real-time services and ON-OFF model, which is single source traffic model, has been used. But ON-OFF model differ from GCRA(Generic Cell Rate Algorithm) controlled traffic in ATM network. In this paper, we analyze the traffic, which is controlled as dual GCRA, and propose TWM(Three-state Worst-case Model), which is new single source traffic model. We also proposed CAC to guarantee peak-to-peak CDV(Cell Delay Variation) based on the TWM. In experiments, ON-OFF model and TWM are compared to show that TWM is superior to ON-Off model in terms of QoS guaranteeing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.486-495
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• 2002

In this paper, we propose a delay reduction method for frame-based packet transmit scheduling algorithm. A high-speed network such as ATM network has to provide some performance guarantees such as bandwidth and delay bound. Framing strategy naturally guarantees bandwidth and enables simple rate-control while having the inherently bad delay characteristics. The proposed delay reduction method uses the same hierarchical frame structure as HRR (Hierarchical Round-Robin) but does not use the static priority scheme such as round-robin. Instead, we use a dynamic priority change scheme so that the delay unfairness between wide bandwidth connection and narrow bandwidth connection can be eliminated. That is, we use FIFO (First-In First-Out) concept to effectively reduce the occurrence of worst-case delay and to enhance delay distribution. We compare the performance for the proposed algorithm with that of HRR. The analytic and simulation results show that HFIFO inherits almost all merits of HRR with fairly better delay characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.6 s.312
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• pp.10-16
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• 2006

This paper proposed a carry lookahead (CLA) circuitry design. It was based on dynamic circuit aiming at delay reduction in an addition of BCD coded decimal numbers. The performance of these decimal adders is analyzed demonstrating their speed improvement. Timing simulation on the proposed decimal addition circuit employing $0.18{\mu}m$ CMOS technology yielded the worst-case delay of 0.83 ns at 16-digit. The proposed scheme showed a speed improvement compared to several schemes for decimal addition.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.12
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• pp.5712-5728
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• 2017

Recently, there are many studies, that considering green wireless cellular networks, have taken the energy consumption of the base station (BS) into consideration. In this work, we first introduce an energy consumption model of multi-mode sharing BS powered by multiple energy sources including renewable energy, local storage and power grid. Then communication load requests of the BS are transformed to energy demand queues, and battery energy level and worst-case delay constraints are considered into the virtual queue to ensure the network QoS when our objective is to minimize the long term electricity cost of BSs. Lyapunov optimization method is applied to work out the optimization objective without knowing the future information of the communication load, real-time electricity market price and renewable energy availability. Finally, linear programming is used, and the corresponding energy efficient scheduling policy is obtained. The performance analysis of our proposed online algorithm based on real-world traces demonstrates that it can greatly reduce one day's electricity cost of individual BS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.1988-1995
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• 2000

ATM 망에서 제공되고 있는 음성, 영상, 데이터와 같은 다양한 서비스는 사용자의 만족도를 수용할 수 있어야 한다는 것을 전제조건으로 한다. 이러한 기본적인 요구사항을 충족시키기 위해서는 노드대 노드간의 자원관리와 오류제어 및 다양한 트래픽의 특성을 고려한 전송 순서의 결정에 해당하는 스케줄링 방법이 요구되어 진다. 본 논문에서는 이러한 기술 요소 중에서 트래픽 설정 단계에서 제공되는 트래픽 특성 및 QoS(Quality of Service) 정보를 바탕으로 교환 노드에서 발생되는 전달 지연 시간에 적응적인 스케줄링 방식을 제시하였다. 이 방식은 멀티미디어 서비스와 같이 혼합된 트래픽 특성을 갖는 구조에서 트래픽 구성비율에 따라 적용되는 지연 여유치를 매우 융통성 있고 효과적으로 조절할 수 있다. 성능분석을 위하여 기존의 스케줄링 방식인 WFQ (Weighted Fair Queueing) 방식과 제안한 스케줄링 방식의 수학적인 분석을 수행하였으며 이 두 방식의 결과식을 비교하여 교환노드에서의 평균 지연과 셀 처리에 관한 성능을 분석하였다. 그리고 수학적 분석에 대한 검증으로는 Simulation tool ARENA 3.0을 이용하여 제안한 알고리즘의 Worst case와 기존의 알고리즘의 성능을 비교하였다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.