• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2004.03a
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• pp.15-25
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• 2004

This paper outlines a new convergence acceleration de-signed to solve scramjet flowfields with zones of re-circulation. Named the “marching-window”, the algorithm consists of performing pseudo-time iterations on a minimal width subdomain composed of a sequence of cross-stream planes of nodes. The upstream boundary of the subdomain is positioned such that all nodes upstream exhibit a residual smaller than the user-specified convergence threshold. The advancement of the downstream boundary follows the advancement of the upstream boundary, except in zones of significant streamwise ellipticity where a streamwise ellipticity sensor ensures its continuous progress. Compared to the standard pseudo-time marching approach, the march-ing-window is here seen to decrease the work required for convergence by up to 24 times for supersonic flows with little streamwise ellipticity and by up to 8 times for supersonic flows with large streamwise separated regions. The memory requirements are observed to be reduced sixfold by not allocating memory to the nodes not included in the computational subdomain. The marching-window satisfies the same convergence criterion as the standard pseudo-time stepping methods, hence resulting in the same converged solution within the tolerance of the user-specified convergence threshold. The extension of the marching-window to the weakly-ionized Navier-Stokes equations is also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.112-112
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• 2009

Temperature dependence of the ferroelectric properties of poly(vinylidefluoride-trifluoroethylene) copolymer thin films are studied with various insulators such as $SrTa_2O_6$ and $La_2O_3$. Thin films of poly(vinylidene fluoridetrifluoroethylene) 75/25 copolymer were prepared by chemical solution deposition on p-Si substrate. Capacitance-voltage (C-V) and current density (J-V) behavior of the Au/P(VDF-TrFE)/Insulator/p-Si structures were studied at ($150-200\;^{\circ}C$) and dielectric constant of the each insulators were measured to be about 15 at $850\;^{\circ}C$ for 10 minutes. Memory window width at 5 V bias the MFIS(metal-ferroelectric-insulator-semiconductor) structure with as deposited films was about 0.5 V at high temperature ($200\;^{\circ}C$). And the memory window width increased as voltage increased from 1 V to 5 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• Journal of the Korean Solar Energy Society
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• v.32 no.3
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• pp.50-58
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• 2012

The objective of this study is to evaluate the lighting dimming rates with various parameters of the building skin in a small office. We compared to simulated workplane illuminance and measured workplane illuminance for the base model. After that, the five veriables(the presence of vertical wall in double skin facade, the presence of windowsill, window to wall ratio(WWR), window visible transmittance, the width of double skin facade) were applied to base model, and we analyzed the simulated lighting energy saving rates. The results are listed as below. The simulated workplane illuminance results are similar to the measurement. Simulated illuminance was smaller than measured illuminance by 16.5%(60 lx). In accordance with applicable building skin parameters, lighting energy saving rate results are summarized as follows. Lighting energy saving rate of case1(windowsill height 0.7m) is higher than that of base case(windowsill and vertical wall) by 7.3% and the lighting energy saving rate of case2(no vertical wall) is higher than that of base case by 7.6% and the lighting energy saving rate of case3(no windowsill and vertical wall) is higher than that of base case by 12.4%. The lighting energy saving rate is increased by 2.3%, when window visible transmittance is increased from 70% to 86%. The lighting energy saving rate is increased by 4.6%, when we changed the WWR 70% to 90%. lighting energy savings rate is increased by 6.5%, when the width of double skin facade is reduced from 1m to 0.3m.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.186-189
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• 2002

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Institute of Interior Design Conference
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• 2001.05a
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• pp.117-120
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• 2001

This study is a preliminary research to develop design principles for environmentally friendly housing. The purposes of study are to investigate the literatures related passive design for summer and theory of ventilation, to analyze the indoor airflow patterns in traditional Korean house during summer, and to propose the design factors for effective passive cooling system. The analysis for airflow patterns was focused on the ‘An bang’and the ‘Dae Chung’in the ‘An Chae’of a traditional house located in Seoul. Field measurements of air temperature and air velocity were carried out at 30 different measuring points with 8 different window-opening conditions. The measurements were taken on the hottest summer days in August 2000. It is concluded that from an environmentally friendly standpoint design factors to control indoor thermal environment by a passive cooling system during the summer are as follows; ceiling structure has thermal performance like a time-lag effect, optimum height and length of eaves which can prevent sunlight and divert airflow toward the sitting level, building arrangement acceptable the prevailing wind, strategic window arrangement which makes cross ventilation possible (especially north-south) at the sitting level, window opening condition which is possible to intersect two cross-ventilation stream at the main living areas, northward windows remaining in shade to create the air pressure difference, and planning building shape like a bracket that has optimum width and depth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.23-26
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• 2003

The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of Families and Better Life
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• v.18 no.2
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• pp.191-202
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• 2000

The purpose of this study was to clarify the wall components of Sarang-taechong in the upper class houses of Chosun dynasty. Physical trace method was used for this study. The samples were taken from the Sarang-taechong of 6 traditional Korean houses; Yunkyungdang, the ancient Chusa estate, Sunkyojang, Chunghyodang, Yangjindant, Unjorn. The makor findings were summarized as follows; 1) The common components of each wall were pillars, sanginbangs(upper horizontal beams), hainbangs (lower horizontal beams), door and windows. Changbangs(wood eave pieces that suported decoration blocks), changyos(a pice of wood fitted between the tops of pillars and upper tori cross beams), and morums(the top wainscot board laid horizontally between the bottom beam and the bottom portion of a window frame) were additional. 2) The composition of every south wall was symmetrical and the other threes were mixed symmetrical and asymmetrical. 3) The image of wall was classified-fine, strong, and modera e, according to the symmetry or asymmetry of wall composition, the width of each components, the kind of window.