• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.385-391
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• 1997

An objection of this study is to develop a measuring circuit of a gauge using radioisotope for compaction control. The gauge developed in this study makes use of radioisotope with the activity exempted from domestic atomic law and consists of measuring circuits for gamma-rays and thermal neutrons, a high voltage supply unit, and a microprocessor. To obtain meaningful numbers of pulse counts, parallel five and two circuits are provided for gamma-rays and thermal neutrons, respectively. Being simple in electrical characteristics of G-M detector for gamma-rays, pulses are counted through only a shaping circuit. Very small pulses generated from He- 3 proportional detector for thermal neutrons are amplified to the maximum of 50 [dB] and a window comparator accepts only pulses with meaning. To minimize effects of natural environmental radiation and electrical noise, circuits are electrostatically shielded and pulses made by ripples are eliminated by taking frequency of high voltage supplied to the circuit and pulse height of ripples into consideration. One-chip microprocessor is applied to process various counts, results are stored and the gauage is made capable to communicate with PC. Enough and meaningful numbers of pulses are counted with the prototype gauage for compaction control.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1252-1262
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• 1988

This paper describes a functional-level design and simulation of Graphics Processor(GP) which can be used in various graphics systems. GP is divided into two parts: One is CPU, and the other is the interface to I/O peripherals. In order to achieve fast execution of graphics instructions, the CPU has special ALU, barrel shifter and window comparator and a FIFO for instruction prefetch. I/O part controls the DRAM and VRAM which constitute the GP's local memory, generates the signals to drive monitor, and communicates with the host processor. The functional simulation of CPU was done on Daisy workstation while the I/O part was designed using GENESIL, a silicon compiler.

• Journal of Biosystems Engineering
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• v.20 no.3
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• pp.226-235
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• 1995

An unmanned speed sprayer was developed using a remote control and an inductive cable guidance systems to protect operators and environment from hazardous pesticides. The sprayer consists of a remote control system, an induction system, obstacle detectors, control actuators and an one-chip microcomputer. The sprayer can be operated by the induction guidance and/or remote control. The following summarize characteristics of the developed speed sprayer. 1) Both the remote control and the induction guidance operation were possible with the developed speed sprayer. 2) Sixteen functions of the forwarding, backing, halting, steering, 3-way valve for nozzles and fan operating etc. were utilized on the remote control system. 3) It was concluded that the DTMF method, having less transmitting error, performed better than the FSK method for an agricultural remote controller. A radio station may be necessary. 4) The digital inductive guidance system, consisting of five low-impedance detection coils and a window comparator circuit, performed better than the analog detecting system, guiding route using inductive voltage differential from tow detection coils.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Journal of Korean Society of Disaster and Security
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• v.14 no.1
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• pp.23-40
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• 2021

In the era of the global coronal 19 pandemic, there is a risk of cross-infection in hospitals at the stage where treatments and vaccines are currently being developed and marketed, so individuals should enhance their acquired immunity and generalize their living systems by the performance of copper ions in the social environment. In order to prevent the spread of infection, the need for anti-bacterial film and its efficacy were analyzed through anti-viral performance tests based on research and development cases of worldwide and immemorial time. he Korea Construction Research Institute (KCL) has received anti-bacterial performance certification and anti-viral test scores from the "National Approval Performance Certification Agency." At the time, NCCP 43326 Human Corona virus (BetaCoV/Korea/KCDC03/2020), which was approved by the Centers for Disease Control and Prevention, was introduced to ensure that the activity rate of infected cells was satisfied in the anti-viral performance test. Anti-proliferation measures for the Corona 19 virus require a quality clinical trial study comparing the experimental group within the glass space where the antiviral copper film is constructed with the comparator of the same condition without copper film.