• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.3
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• pp.237-246
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• 2022

This paper proposes a method to adjust the turn ratio of a transformer for the high-efficiency operation of an LLC converter with a wide input range in a wired/wireless integrated charging system for electric vehicles. The characteristics of the inductive power transfer converter in the integrated charging system are analyzed to design the LLC converter, and the DC-link voltage range is derived. The aspect of voltage gain following each parameter of the LLC converter is analyzed, and the resonant network and transformer are designed. Based on the designed parameters, the feasibility of the design and control method is verified by implementing the operation of the LLC converter according to the DC-link and battery voltages.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.80-87
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• 2013

A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.6
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• pp.570-579
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• 2009

In this paper, we presented a Vt-DRO with a wide electrical frequency tuning range, using open-loop gain method. The Vt-DRO was composed of 3-stages, resonator, amplifier and phase shifter. In order to satisfy an oscillation condition, we determined magnitude and phase of each stage. The measured S-parameter of cascaded 3-stages shows open-loop oscillation condition. Also, using measured open loop group delay, we derived the relation for electrical frequency tuning range. The Vt-DRO was implemented by connecting the input and the output of the designed open-loop and resulted in closed-loop. As a results, tuning-range of Vt-DRO is 82 MHz, which is close to the predicted results for tuning voltage 0${\sim}$10 V and shows linear frequency tuning at the center frequency of 5.3 GHz. The phase noise is -104 ${\pm}$1 dBc/Hz at 100 kHz offset frequency and power is 5.86${\pm}$1 dBm respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• BioChip Journal
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• v.12 no.4
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• pp.332-339
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• 2018

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.48-56
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• 2015

There is a wide variety of system and applications in the power system. However, they have compatibility issues because they use different data standard and communication method. With the introduction of the smart grid, power system has been grow and diversified. Therefore power system need to be compatible with each other and the interoperability between applications is increasingly important. Thus, the IEC established IEC61970 and CIM Standard data exchange model for interoperability and system integration. Server-Client system was constructed which using CIM HSDA(Part4), a standard communication model, presented in IEC 619710. Also, self-developed real-time voltage stability analysis application and contingency analysis application was used. CIM HSDA was used for data input and real-time analysis. Tolerance of result which is in the range of allowable derived by Perform real-time voltage stability and contingency analysis of Jeju power system, and then compare it's result with PSS/E result.

• Korean Journal of Optics and Photonics
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• v.14 no.1
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• pp.12-16
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• 2003

This paper presents a compensation method for a temperature-dependent gain tilt in L-band erbium-doped fiber amplifier using a voltage-controlled attenuator. The gain tilts in the L-band of 1570-1605 nm due to a temperature change have negative slopes, whereas they have positive slopes for the increasing optical input powers in a saturation region. The proposed method utilizes these opposite gain variations to compensate for the gain tilt over a wide range of temperature. While applying forty channels with a channel spacing of 100 GHz in the L-band and changing the ambient temperature from 0 to $50^{\circ}C$, the compensation method maintained the gain deviation within 1 dB.

• Smart Structures and Systems
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• v.18 no.5
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• pp.1005-1028
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• 2016

Two novel semi-active control methods for a seismically excited nonlinear benchmark building equipped with magnetorheological dampers are presented and evaluated in this paper. While a primary controller is designed to estimate the optimal control force of a magnetorheological (MR) damper, the required voltage input for the damper to produce such desired control force is achieved using two different methods. The first technique uses an optimal compact Takagi-Sugeno-Kang (TSK) fuzzy inverse model of MR damper to predict the required voltage to actuate the MR dampers (TSKFInv). The other voltage regulator introduced here works based on the maximum and minimum capacities of MR damper at each time-step (MaxMin). Both semi-active algorithms developed here, use acceleration feedback only. The results demonstrate that both TSKFInv and MaxMin algorithms are quite effective in seismic response reduction for wide range of motions from moderate to severe seismic events, compared with the passive systems and performs better than original and Modified clipped optimal controller systems, known as COC and MCOC.