• 한국표면공학회지
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• 제28권1호
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• pp.55-63
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• 1995

Alkaline solutions such as $NH_4$OH, choline and TMAH (($CH_3$)$_4$NOH) have been introduced in semiconductor wet processing of silicon wafers to control ionic and particulate impurities following etching in acidic solutions. These chemicals usually mixed with hydrogen peroxide and/or surfactants to control the etch rate of silicon. The highest etch rate was observed in $NH_4$OH solutions at a pH in alkaline solutions. It indicates that the etch rate depends on the content of $OH^{-}$ as well as cations of alkaline solutions. STM/AFM techniques were used to characterize the effect of alkaline solutions on silicon surface roughness. In SC1 (mixture of $NH_4$OH : $H_2$$O_2$ : $H_2$O) solutions, the reduction of the ammonium hydroxide proportion from 1 to 0.1 decreased the surface roughness ($R_{rms}$) from 6.4 to $0.8\AA$. The addition of $H_2$$O_2$ and surfactants to choline and TMAH reduced the values of $R_{p-v}$ and $R_{rms}$ significantly. $H_2$$_O2$ and surfactants added in alkaline solutions passivate bare silicon surfaces by the oxidation and adsorption, respectively. The passivation of surfaces in alkaline solutions resulted in lower etch rate of silicon thereby provided smoother surfaces.s.ces.s.

• 한국진공학회지
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• 제8권4A호
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• pp.490-495
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• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.926-929
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• 2007

A significant progress has been made in the characterization of zinc oxide (ZnO) semiconductor as a new semiconductor layer instead of amorphous Si semiconductor used in thin film transistor due to its high electron mobility at low deposition temperature which is quite suitable for flexible display and OLED devices. The wet pattering of ZnO is another important issue with regard to mass production of ZnO thin film transistor device. However, the wet behavior of ZnO thin film in aqueous wet etching solutions conventionally used un TFT industry has not been reported yet, in this work, wet corrosion behavior of RF magnetron sputtered ZnO thin film in various wet solutions such as phosphoric and nitric acid solutions was studied using by electrochemical analysis. The effects of deposition parameters such as RF power and oxygen partial pressure on corrosion rate are also examined.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1649-1652
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (${\alpha}$- Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated because the 2.5 um fine pattern formation technique is combined with high thermal photo-resist (PR) development. In addition, a novel concept of unique ${\alpha}$-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um finepatterning is a considerably significant technology to obtain higher aperture ratio for higher resolution ${\alpha}$-Si TFT-LCD panel realization.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.150-150
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• 2008

본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.

• 한국광학회지
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• 제8권4호
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• pp.345-352
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• 1997

최신(4GDRAM)의 MASK design에서는 전자기파의 산란에 의한 효과를 고려해 주는 것이 매우 중요하다. 이를 위하여 시간 영역에서의 요한 차분법을 도입하여 직접 마스크 함수를 계산하였다. 새롭게 도입한 마스크 함수를 사용함으로써 마스크와 렌즈의 효과뿐만 아니라, submicron 노광용 위상 변이 마스크의 식각된 옆벽에서의 산란효과를 정확하게 설명할 수 있었다. 산란효과를 줄이기 위해 변형된 마스크의 형태에 따른 특성을 살펴보았고, dual etch back에 의한 마스크 변형이 가장 좋은 공정 여유도를 제공함을 확인하였다.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1271-1276
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• 2004

Two-dimensionally arrayed nanocolumn lattices were fabricated by using double-exposure laser holographic method. The hexagonal lattice was formed by rotating the sample with 60 degree while the square lattice by 90 degree before the second laser-exposure. The reactive ion etching for a typical time of 30 min using CH$_4$/H$_2$ plasma enhanced the aspect-ratio by more than 1.5 with a slight increase of the bottom width of columns. The etch-damage was observed by photoluminescence (PL) spectroscopy which was removed by the wet chemical etching using HBr/$H_2O$$_2$/$H_2O$ solution, leading into the enhanced PL intensities of the PCs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1977-1979
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• 1996

Single-crystaIline silicon diaphgrams and features are fabricated without using an etch stop process. The process involves vertical dry etching, double-sided alignment, followed by wet-chemical etching from the back side. The abvantages of this process are that $5{\sim}50{\mu}m$ diaphgrams and features can be fabricated accurately and inexpensively. In addition, since no impurity-based process is introduced, highly uniform and homogenous properties can be achieved

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.147-148
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• 1998

In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.