• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.7
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• pp.3455-3474
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• 2018

As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

• Geomechanics and Engineering
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• v.8 no.4
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• pp.477-493
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• 2015

In rock drilling, the most important characteristic to clarify is the wear of the drill bits. The reason that the rock drill bits fail with time is wear. In dry sliding contact adhesive wear deteriorates the materials in contact, quickly, and is the result of shear fracture in the momentary contact joins between the surfaces. This paper aims at presenting an overview of the assessment of WC/Co cemented carbide (CC) tricone bit in rotary drilling. To study wear of these bits, two approaches have been used in this research. Firstly, the new bits were weighted before they mounted on the drill rigs and also after completion their useful life to obtain bit weight loss percentage. The characteristics of the rock types drilled by using such this bit were measured, simultaneously. Alternatively, to measure contact wear, namely, matrix wear a micrometer has been used with a resolution of 0.02 mm at different direction on the tricone bits. Equivalent quartz content (EQC), net quartz content (QC), muscovite content (Mu), coarseness index (CI) of drill cuttings and compressive strength of rocks (UCS) were obtained along with thin sections to investigate mineralogical properties in detail. The correlation between effective parameters and bit wear were obtained as result of this study. It was observed that UCS shows no significant correlation with bit wear. By increasing CI and cutting size of rocks wear of bit increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• The KIPS Transactions:PartB
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• v.11B no.4
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• pp.395-402
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• 2004

In this paper, we proposed a new method of the large capacity steganography using adaptive threshold on bit planes. Applying fixing threshold, if we insert information into all bit planes, all bit planes showed different image quality. Therefore, we first defined the bit plane weight to solve the fixing threshold problem. We then proposed a new adaptive threshold method using the bit plane weight and the average complexity to increase insertion capacity adaptively. In the experiment, we inserted information into the standard images with the same image quality and same insertion capacity, and we analyzed the insertion capacity and image duality. As a result, the proposed method increased the insertion capacity of about 6% and improved the image quality of about 24dB than fixed threshold method.

• Journal of Communications and Networks
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• v.7 no.4
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• pp.462-470
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• 2005

We propose a multi-rate and multi-BEP transmission scheme using adaptive overlapping pulse-position modulator (OPPM) and optical power controller in optical code division multiple access (CDMA) networks. The proposed system achieves the multi-rate and multi-BEP transmission by accommodating users with different values of OPPM parameter and transmitted power in the same network. The proposed scheme has advantages that the system is not required to change the code length and number of weight depending on the required bit rate of a user and the difference of bit rates does not have so much effect on the bit error probabilities (BEPs). Moreover, the difference of transmitted powers does not cause the change of bit rate. We analyze the BEPs of the four multimedia service classes corresponding to the com­binations of high/low-rates and low/high-BEPs and show that the proposed scheme can easily achieve distinct differentiation of the service classes with the simple system configuration.

• Journal of Korean Medicine Rehabilitation
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• v.33 no.3
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• pp.1-15
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• 2023

Objectives We aimed to find out the improvement effect of Baekhogainsam-tang (Baihu Jia Renshen-tang, BIT) on metabolic syndrome and alteration of microbiota and gene expression. Methods We used male C57BI/6 mice and randomly assigned them into three groups. Normal control group was fed 10% kcal% fat diet, high-fat diet (HFD) group was fed 45% kcal% fat diet and 10% fructose water. BIT group was fed same diet as HFD group and treated by BIT for once daily, 6 days per week, total 8 weeks. We measured their body weight and food intake every week and performed oral glucose tolerance test 1 week before the end of the study. Then we collected the blood sample to measure triglyceride, total cholesterol, high-density lipoprotein cholesterol, insulin, and hemoglobin A1c. We harvested tissue of liver, muscle, fat, and large intestine for quantitative polymerase chain reaction (qPCR) and histopathological examination. Fresh fecal samples were collected from each animal to verify alterations of gut microbiota and we used RNA from liver tissue for microarray analysis. Results The body weight and fat weight of BIT group were reduced compared to HFD group. The qPCR markers usually up-regulated in metabolic syndrome were decreased in BIT group. Bacteroides were higher in BIT group than other groups. There were also differences in gene expressions between two groups such as Cyp3a11 and Scd1. Conclusions We could find out BIT can ameliorate metabolic syndrome and suggest its effect is related to gut microbiota composition and gene expression pattern.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.11
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• pp.1959-1975
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• 2011

Adaptive Bit Loading (ABL) in Multiple-Input Multiple-Output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) is often used to achieve the desired Bit Error Rate (BER) performance in wireless systems. In this paper, we discuss some of the bit loading algorithms, compare them in terms of the BER performance, and present an effective and concise Adaptive Grouped Loading (AGL) algorithm. Furthermore, we propose a "weight factor" for loading algorithm to converge rapidly to the final solution for various data rate with variable Signal to Noise Ratio (SNR) gaps. In particular, we consider the bit loading in near optimal Singular Value Decomposition (SVD) based MIMO-OFDM system. While using SVD based system, the system requires perfect Channel State Information (CSI) of channel transfer function at the transmitter. This scenario of SVD based system is taken as an ideal case for the comparison of loading algorithms and to show the actual enhancement achievable by our AGL algorithm. Irrespective of the CSI requirement imposed by the mode of the system itself, ABL demands high level of feedback. Grouped Loading (GL) would reduce the feedback requirement depending upon the group size. However, this also leads to considerable degradation in BER performance. In our AGL algorithm, groups are formed with a number of consecutive sub-channels belonging to the same transmit antenna, with individual gains satisfying predefined criteria. Simulation results show that the proposed "weight factor" leads a loading algorithm to rapid convergence for various data rates with variable SNR gap values and AGL requires much lesser CSI compared to GL for the same BER performance.