• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.5 no.2
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• pp.130-140
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• 1993

Average particle deposition velocity toward a horizontal semiconductor wafer in vertical airflow is measured by a wafer surface scanner(PMS SAS-3600). Use of wafer surface scanner requires very short exposure time normally ranging from 10 to 30 minutes, and hence makes repetition of experiment much easier. Polystyrene latex (PSL) spheres of diameter between 0.2 and $1.0{\mu}m$ are used. The present range of particle sizes is very important in controlling particle deposition on a wafer surface in industrial applications. For the present experiment, convection, diffusion, and sedimentation comprise important agents for deposition mechanisms. To investigate confidence interval of experimental data, mean and standard deviation of average deposition velocities are obtained from more than ten data set for each PSL sphere size. It is found that the distribution of mean of average deposition velocities from the measurement agrees well with the predictions of Liu and Ahn(1987) and Emi et al.(1989).

• Particle and aerosol research
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• v.5 no.1
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• pp.17-27
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• 2009

Particle deposition on a semiconductor wafer larger than 100 mm was studied experimentally and numerically. Particularly the electrostatic effect on particle deposition velocity was investigated. The experimental apparatus consisted of a particle generation system, a particle deposition chamber and a wafer surface scanner. Experimental data of particle deposition velocity were obtained for a semiconductor wafer of 200 mm diameter with the applied voltage of 5,000 V and PSL particles of the sizes between 83 and 495 nm. The experimental data of particle deposition velocity were compared with the present numerical results and the existing experimental data for a 100 mm wafer by Ye et al. (1991) and Opiolka et al. (1994). The present numerical method took into consideration the particle transport mechanisms of convection, Brownian diffusion, gravitational settling and electrostatic attraction in an Eulerian frame of reference. Based on the comparison of the present experimental and numerical results with the existing experimental results the present experimental method for a 200 mm semiconductor wafer was found to be able to present reasonable data.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.5
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• pp.70-75
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• 2000

After the patterning and probe process of wafer have been achieved, the dicing process is necessary to separate chips from a wafer. The dicing process cuts a wafer to lengthwise and crosswise direction to make many chips by using narrow circular rotating diamond blade. But inferior goods are made under the influence of complex dicing environment such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using feature extraction in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, two features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision. a threshold method is adopted to classify the dicing process into normal and abnormal dicing. Experiment have been performed for GaAs semiconductor wafer. Based upon observation of the experimental results, the proposed scheme shown a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 12.8%.

• Particle and aerosol research
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• v.14 no.2
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• pp.41-47
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• 2018

Numerical analysis was conducted to characterize particle deposition onto a heated horizontal semiconductor wafer in vacuum environment. In order to calculate the properties of gas surrounding the wafer, the gas was assumed to obey the ideal gas law. Particle transport mechanisms considered in the present study were convection, Brownian diffusion, gravitational settling and thermophoresis. Averaged particle deposition velocities on the upper surface of the wafer were calculated with respect to particle size, based on the numerical results from the particle concentration equation in the Eulerian frame of reference. The deposition velocities were obtained for system pressures of 1000 Pa~1 atm, wafer heating of 0~5 K and particle sizes of $2{\sim}10^4nm$. The present numerical results showed good agreement with the available experimental ones.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.224-225
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• 2000

Transparent and hard materials such as sapphire are used for many industrial applications as optical windows, hard materials on mechanical contact against abrasion, and substrate materials for opto-electronic semiconductor devices such as blue LED and blue LD etc. The materials should be cut along the proper shapes possible to be used for each application. In case of blue LED, the blue LED wafer should be cut to thousands of blue LED pieces at the final stage of the manufacturing process. The process of cutting the wafer is usually divided into two steps. The wafer is scribed along the proper shapes in the first step. It is inserted between transparent flexible sheets for easy handling. And then, it is broken and split in the next step. Harder materials such as diamonds are usually used to scribe the wafer, while it has a problem of low depth of scribing and abrasion of the harder material itself. The low depth of scribing can induce failure in breaking the wafer along the scribed line. It was also known that the expensive diamond tip should be replaced frequently for the abrasion. (omitted)